Lines Matching defs:tup
147 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);
148 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);
149 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
152 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup,
155 return readl(tup->uport.membase + (reg << tup->uport.regshift));
158 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val,
161 writel(val, tup->uport.membase + (reg << tup->uport.regshift));
171 struct tegra_uart_port *tup = to_tegra_uport(u);
182 if (tup->enable_modem_interrupt)
187 static void set_rts(struct tegra_uart_port *tup, bool active)
191 mcr = tup->mcr_shadow;
196 if (mcr != tup->mcr_shadow) {
197 tegra_uart_write(tup, mcr, UART_MCR);
198 tup->mcr_shadow = mcr;
202 static void set_dtr(struct tegra_uart_port *tup, bool active)
206 mcr = tup->mcr_shadow;
211 if (mcr != tup->mcr_shadow) {
212 tegra_uart_write(tup, mcr, UART_MCR);
213 tup->mcr_shadow = mcr;
217 static void set_loopbk(struct tegra_uart_port *tup, bool active)
219 unsigned long mcr = tup->mcr_shadow;
226 if (mcr != tup->mcr_shadow) {
227 tegra_uart_write(tup, mcr, UART_MCR);
228 tup->mcr_shadow = mcr;
234 struct tegra_uart_port *tup = to_tegra_uport(u);
237 tup->rts_active = !!(mctrl & TIOCM_RTS);
238 set_rts(tup, tup->rts_active);
241 set_dtr(tup, enable);
244 set_loopbk(tup, enable);
249 struct tegra_uart_port *tup = to_tegra_uport(u);
252 lcr = tup->lcr_shadow;
257 tegra_uart_write(tup, lcr, UART_LCR);
258 tup->lcr_shadow = lcr;
264 * @tup: Tegra serial port data structure.
270 static void tegra_uart_wait_cycle_time(struct tegra_uart_port *tup,
273 if (tup->current_baud)
274 udelay(DIV_ROUND_UP(cycles * 1000000, tup->current_baud * 16));
278 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup,
281 if (tup->current_baud)
282 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000,
283 tup->current_baud));
286 static int tegra_uart_wait_fifo_mode_enabled(struct tegra_uart_port *tup)
292 iir = tegra_uart_read(tup, UART_IIR);
301 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits)
303 unsigned long fcr = tup->fcr_shadow;
306 if (tup->rts_active)
307 set_rts(tup, false);
309 if (tup->cdata->allow_txfifo_reset_fifo_mode) {
311 tegra_uart_write(tup, fcr, UART_FCR);
314 tegra_uart_write(tup, fcr, UART_FCR);
317 tegra_uart_write(tup, fcr, UART_FCR);
319 tegra_uart_write(tup, fcr, UART_FCR);
320 if (tup->cdata->fifo_mode_enable_status)
321 tegra_uart_wait_fifo_mode_enabled(tup);
325 tegra_uart_read(tup, UART_SCR);
332 tegra_uart_wait_cycle_time(tup, 32);
335 lsr = tegra_uart_read(tup, UART_LSR);
341 if (tup->rts_active)
342 set_rts(tup, true);
345 static long tegra_get_tolerance_rate(struct tegra_uart_port *tup,
350 for (i = 0; i < tup->n_adjustable_baud_rates; ++i) {
351 if (baud >= tup->baud_tolerance[i].lower_range_baud &&
352 baud <= tup->baud_tolerance[i].upper_range_baud)
354 tup->baud_tolerance[i].tolerance) / 10000);
360 static int tegra_check_rate_in_range(struct tegra_uart_port *tup)
364 diff = ((long)(tup->configured_rate - tup->required_rate) * 10000)
365 / tup->required_rate;
366 if (diff < (tup->cdata->error_tolerance_low_range * 100) ||
367 diff > (tup->cdata->error_tolerance_high_range * 100)) {
368 dev_err(tup->uport.dev,
376 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud)
384 if (tup->current_baud == baud)
387 if (tup->cdata->support_clk_src_div) {
389 tup->required_rate = rate;
391 if (tup->n_adjustable_baud_rates)
392 rate = tegra_get_tolerance_rate(tup, baud, rate);
394 ret = clk_set_rate(tup->uart_clk, rate);
396 dev_err(tup->uport.dev,
400 tup->configured_rate = clk_get_rate(tup->uart_clk);
402 ret = tegra_check_rate_in_range(tup);
406 rate = clk_get_rate(tup->uart_clk);
410 spin_lock_irqsave(&tup->uport.lock, flags);
411 lcr = tup->lcr_shadow;
413 tegra_uart_write(tup, lcr, UART_LCR);
415 tegra_uart_write(tup, divisor & 0xFF, UART_TX);
416 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER);
419 tegra_uart_write(tup, lcr, UART_LCR);
422 tegra_uart_read(tup, UART_SCR);
423 spin_unlock_irqrestore(&tup->uport.lock, flags);
425 tup->current_baud = baud;
428 tegra_uart_wait_sym_time(tup, 2);
432 static char tegra_uart_decode_rx_error(struct tegra_uart_port *tup,
441 tup->uport.icount.overrun++;
442 dev_dbg(tup->uport.dev, "Got overrun errors\n");
446 tup->uport.icount.parity++;
447 dev_dbg(tup->uport.dev, "Got Parity errors\n");
450 tup->uport.icount.frame++;
451 dev_dbg(tup->uport.dev, "Got frame errors\n");
458 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR);
459 if (tup->uport.ignore_status_mask & UART_LSR_BI)
462 tup->uport.icount.brk++;
463 dev_dbg(tup->uport.dev, "Got Break\n");
465 uart_insert_char(&tup->uport, lsr, UART_LSR_OE, 0, flag);
481 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes)
483 struct circ_buf *xmit = &tup->uport.state->xmit;
488 if (tup->cdata->tx_fifo_full_status) {
489 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
493 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX);
495 tup->uport.icount.tx++;
499 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup,
505 tup->tx_in_progress = TEGRA_UART_TX_PIO;
506 tup->tx_bytes = bytes;
507 tup->ier_shadow |= UART_IER_THRI;
508 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
513 struct tegra_uart_port *tup = args;
514 struct circ_buf *xmit = &tup->uport.state->xmit;
519 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
520 count = tup->tx_bytes_requested - state.residue;
521 async_tx_ack(tup->tx_dma_desc);
522 spin_lock_irqsave(&tup->uport.lock, flags);
523 uart_xmit_advance(&tup->uport, count);
524 tup->tx_in_progress = 0;
526 uart_write_wakeup(&tup->uport);
527 tegra_uart_start_next_tx(tup);
528 spin_unlock_irqrestore(&tup->uport.lock, flags);
531 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup,
534 struct circ_buf *xmit = &tup->uport.state->xmit;
537 tup->tx_bytes = count & ~(0xF);
538 tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail;
540 dma_sync_single_for_device(tup->uport.dev, tx_phys_addr,
541 tup->tx_bytes, DMA_TO_DEVICE);
543 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan,
544 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV,
546 if (!tup->tx_dma_desc) {
547 dev_err(tup->uport.dev, "Not able to get desc for Tx\n");
551 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete;
552 tup->tx_dma_desc->callback_param = tup;
553 tup->tx_in_progress = TEGRA_UART_TX_DMA;
554 tup->tx_bytes_requested = tup->tx_bytes;
555 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc);
556 dma_async_issue_pending(tup->tx_dma_chan);
560 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup)
564 struct circ_buf *xmit = &tup->uport.state->xmit;
566 if (!tup->current_baud)
574 if (tup->use_tx_pio || count < TEGRA_UART_MIN_DMA)
575 tegra_uart_start_pio_tx(tup, count);
577 tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail));
579 tegra_uart_start_tx_dma(tup, count);
585 struct tegra_uart_port *tup = to_tegra_uport(u);
588 if (!uart_circ_empty(xmit) && !tup->tx_in_progress)
589 tegra_uart_start_next_tx(tup);
594 struct tegra_uart_port *tup = to_tegra_uport(u);
599 if (!tup->tx_in_progress) {
600 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
610 struct tegra_uart_port *tup = to_tegra_uport(u);
614 if (tup->tx_in_progress != TEGRA_UART_TX_DMA)
617 dmaengine_pause(tup->tx_dma_chan);
618 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
619 dmaengine_terminate_all(tup->tx_dma_chan);
620 count = tup->tx_bytes_requested - state.residue;
621 async_tx_ack(tup->tx_dma_desc);
622 uart_xmit_advance(&tup->uport, count);
623 tup->tx_in_progress = 0;
626 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup)
628 struct circ_buf *xmit = &tup->uport.state->xmit;
630 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes);
631 tup->tx_in_progress = 0;
633 uart_write_wakeup(&tup->uport);
634 tegra_uart_start_next_tx(tup);
637 static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup,
645 lsr = tegra_uart_read(tup, UART_LSR);
649 flag = tegra_uart_decode_rx_error(tup, lsr);
653 ch = (unsigned char) tegra_uart_read(tup, UART_RX);
654 tup->uport.icount.rx++;
656 if (uart_handle_sysrq_char(&tup->uport, ch))
659 if (tup->uport.ignore_status_mask & UART_LSR_DR)
666 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup,
676 tup->uport.icount.rx += count;
678 if (tup->uport.ignore_status_mask & UART_LSR_DR)
681 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys,
684 ((unsigned char *)(tup->rx_dma_buf_virt)), count);
687 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n");
689 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
693 static void do_handle_rx_pio(struct tegra_uart_port *tup)
695 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
696 struct tty_port *port = &tup->uport.state->port;
698 tegra_uart_handle_rx_pio(tup, port);
705 static void tegra_uart_rx_buffer_push(struct tegra_uart_port *tup,
708 struct tty_port *port = &tup->uport.state->port;
711 async_tx_ack(tup->rx_dma_desc);
712 count = tup->rx_bytes_requested - residue;
715 tegra_uart_copy_rx_to_tty(tup, port, count);
717 do_handle_rx_pio(tup);
722 struct tegra_uart_port *tup = args;
723 struct uart_port *u = &tup->uport;
730 status = dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
733 dev_dbg(tup->uport.dev, "RX DMA is in progress\n");
738 if (tup->rts_active)
739 set_rts(tup, false);
741 tup->rx_dma_active = false;
742 tegra_uart_rx_buffer_push(tup, 0);
743 tegra_uart_start_rx_dma(tup);
746 if (tup->rts_active)
747 set_rts(tup, true);
753 static void tegra_uart_terminate_rx_dma(struct tegra_uart_port *tup)
757 if (!tup->rx_dma_active) {
758 do_handle_rx_pio(tup);
762 dmaengine_pause(tup->rx_dma_chan);
763 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
764 dmaengine_terminate_all(tup->rx_dma_chan);
766 tegra_uart_rx_buffer_push(tup, state.residue);
767 tup->rx_dma_active = false;
770 static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup)
773 if (tup->rts_active)
774 set_rts(tup, false);
776 tegra_uart_terminate_rx_dma(tup);
778 if (tup->rts_active)
779 set_rts(tup, true);
782 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup)
786 if (tup->rx_dma_active)
789 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan,
790 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM,
792 if (!tup->rx_dma_desc) {
793 dev_err(tup->uport.dev, "Not able to get desc for Rx\n");
797 tup->rx_dma_active = true;
798 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete;
799 tup->rx_dma_desc->callback_param = tup;
800 tup->rx_bytes_requested = count;
801 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc);
802 dma_async_issue_pending(tup->rx_dma_chan);
808 struct tegra_uart_port *tup = to_tegra_uport(u);
811 msr = tegra_uart_read(tup, UART_MSR);
816 tup->uport.icount.rng++;
818 tup->uport.icount.dsr++;
821 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD);
824 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS);
829 struct tegra_uart_port *tup = data;
830 struct uart_port *u = &tup->uport;
839 iir = tegra_uart_read(tup, UART_IIR);
841 if (!tup->use_rx_pio && is_rx_int) {
842 tegra_uart_handle_rx_dma(tup);
843 if (tup->rx_in_progress) {
844 ier = tup->ier_shadow;
847 tup->ier_shadow = ier;
848 tegra_uart_write(tup, ier, UART_IER);
851 tegra_uart_start_rx_dma(tup);
863 tup->ier_shadow &= ~UART_IER_THRI;
864 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
865 tegra_uart_handle_tx_pio(tup);
870 if (!tup->use_rx_pio) {
871 is_rx_int = tup->rx_in_progress;
873 ier = tup->ier_shadow;
876 tup->ier_shadow = ier;
877 tegra_uart_write(tup, ier, UART_IER);
882 if (!tup->use_rx_pio) {
883 is_rx_start = tup->rx_in_progress;
884 tup->ier_shadow &= ~UART_IER_RDI;
885 tegra_uart_write(tup, tup->ier_shadow,
888 do_handle_rx_pio(tup);
893 tegra_uart_decode_rx_error(tup,
894 tegra_uart_read(tup, UART_LSR));
906 struct tegra_uart_port *tup = to_tegra_uport(u);
907 struct tty_port *port = &tup->uport.state->port;
910 if (tup->rts_active)
911 set_rts(tup, false);
913 if (!tup->rx_in_progress)
916 tegra_uart_wait_sym_time(tup, 1); /* wait one character interval */
918 ier = tup->ier_shadow;
921 tup->ier_shadow = ier;
922 tegra_uart_write(tup, ier, UART_IER);
923 tup->rx_in_progress = 0;
925 if (!tup->use_rx_pio)
926 tegra_uart_terminate_rx_dma(tup);
928 tegra_uart_handle_rx_pio(tup, port);
931 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup)
934 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud);
935 unsigned long fifo_empty_time = tup->uport.fifosize * char_time;
942 tegra_uart_write(tup, 0, UART_IER);
944 lsr = tegra_uart_read(tup, UART_LSR);
946 msr = tegra_uart_read(tup, UART_MSR);
947 mcr = tegra_uart_read(tup, UART_MCR);
949 dev_err(tup->uport.dev,
958 msr = tegra_uart_read(tup, UART_MSR);
959 mcr = tegra_uart_read(tup, UART_MCR);
962 dev_err(tup->uport.dev,
966 lsr = tegra_uart_read(tup, UART_LSR);
970 spin_lock_irqsave(&tup->uport.lock, flags);
972 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
973 tup->current_baud = 0;
974 spin_unlock_irqrestore(&tup->uport.lock, flags);
976 tup->rx_in_progress = 0;
977 tup->tx_in_progress = 0;
979 if (!tup->use_rx_pio)
980 tegra_uart_dma_channel_free(tup, true);
981 if (!tup->use_tx_pio)
982 tegra_uart_dma_channel_free(tup, false);
984 clk_disable_unprepare(tup->uart_clk);
987 static int tegra_uart_hw_init(struct tegra_uart_port *tup)
991 tup->fcr_shadow = 0;
992 tup->mcr_shadow = 0;
993 tup->lcr_shadow = 0;
994 tup->ier_shadow = 0;
995 tup->current_baud = 0;
997 ret = clk_prepare_enable(tup->uart_clk);
999 dev_err(tup->uport.dev, "could not enable clk\n");
1004 reset_control_assert(tup->rst);
1006 reset_control_deassert(tup->rst);
1008 tup->rx_in_progress = 0;
1009 tup->tx_in_progress = 0;
1029 tup->fcr_shadow = UART_FCR_ENABLE_FIFO;
1031 if (tup->use_rx_pio) {
1032 tup->fcr_shadow |= UART_FCR_R_TRIG_11;
1034 if (tup->cdata->max_dma_burst_bytes == 8)
1035 tup->fcr_shadow |= UART_FCR_R_TRIG_10;
1037 tup->fcr_shadow |= UART_FCR_R_TRIG_01;
1040 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B;
1041 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1044 tegra_uart_read(tup, UART_SCR);
1046 if (tup->cdata->fifo_mode_enable_status) {
1047 ret = tegra_uart_wait_fifo_mode_enabled(tup);
1049 dev_err(tup->uport.dev,
1060 tegra_uart_wait_cycle_time(tup, 3);
1068 ret = tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD);
1070 dev_err(tup->uport.dev, "Failed to set baud rate\n");
1073 if (!tup->use_rx_pio) {
1074 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR;
1075 tup->fcr_shadow |= UART_FCR_DMA_SELECT;
1076 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1078 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1080 tup->rx_in_progress = 1;
1096 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | UART_IER_RDI;
1102 if (!tup->use_rx_pio)
1103 tup->ier_shadow |= TEGRA_UART_IER_EORD;
1105 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1109 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
1113 dmaengine_terminate_all(tup->rx_dma_chan);
1114 dma_release_channel(tup->rx_dma_chan);
1115 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE,
1116 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys);
1117 tup->rx_dma_chan = NULL;
1118 tup->rx_dma_buf_phys = 0;
1119 tup->rx_dma_buf_virt = NULL;
1121 dmaengine_terminate_all(tup->tx_dma_chan);
1122 dma_release_channel(tup->tx_dma_chan);
1123 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys,
1125 tup->tx_dma_chan = NULL;
1126 tup->tx_dma_buf_phys = 0;
1127 tup->tx_dma_buf_virt = NULL;
1131 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup,
1140 dma_chan = dma_request_chan(tup->uport.dev, dma_to_memory ? "rx" : "tx");
1143 dev_err(tup->uport.dev,
1149 dma_buf = dma_alloc_coherent(tup->uport.dev,
1153 dev_err(tup->uport.dev,
1158 dma_sync_single_for_device(tup->uport.dev, dma_phys,
1161 dma_sconfig.src_addr = tup->uport.mapbase;
1163 dma_sconfig.src_maxburst = tup->cdata->max_dma_burst_bytes;
1164 tup->rx_dma_chan = dma_chan;
1165 tup->rx_dma_buf_virt = dma_buf;
1166 tup->rx_dma_buf_phys = dma_phys;
1168 dma_phys = dma_map_single(tup->uport.dev,
1169 tup->uport.state->xmit.buf, UART_XMIT_SIZE,
1171 if (dma_mapping_error(tup->uport.dev, dma_phys)) {
1172 dev_err(tup->uport.dev, "dma_map_single tx failed\n");
1176 dma_buf = tup->uport.state->xmit.buf;
1177 dma_sconfig.dst_addr = tup->uport.mapbase;
1180 tup->tx_dma_chan = dma_chan;
1181 tup->tx_dma_buf_virt = dma_buf;
1182 tup->tx_dma_buf_phys = dma_phys;
1187 dev_err(tup->uport.dev,
1189 tegra_uart_dma_channel_free(tup, dma_to_memory);
1198 struct tegra_uart_port *tup = to_tegra_uport(u);
1201 if (!tup->use_tx_pio) {
1202 ret = tegra_uart_dma_channel_allocate(tup, false);
1210 if (!tup->use_rx_pio) {
1211 ret = tegra_uart_dma_channel_allocate(tup, true);
1219 ret = tegra_uart_hw_init(tup);
1226 dev_name(u->dev), tup);
1234 if (!tup->use_rx_pio)
1235 tegra_uart_dma_channel_free(tup, true);
1237 if (!tup->use_tx_pio)
1238 tegra_uart_dma_channel_free(tup, false);
1248 struct tegra_uart_port *tup = to_tegra_uport(u);
1250 tup->tx_bytes = 0;
1251 if (tup->tx_dma_chan)
1252 dmaengine_terminate_all(tup->tx_dma_chan);
1257 struct tegra_uart_port *tup = to_tegra_uport(u);
1259 tegra_uart_hw_deinit(tup);
1260 free_irq(u->irq, tup);
1265 struct tegra_uart_port *tup = to_tegra_uport(u);
1267 if (tup->enable_modem_interrupt) {
1268 tup->ier_shadow |= UART_IER_MSI;
1269 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1276 struct tegra_uart_port *tup = to_tegra_uport(u);
1281 struct clk *parent_clk = clk_get_parent(tup->uart_clk);
1283 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF;
1290 if (tup->rts_active)
1291 set_rts(tup, false);
1294 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER);
1295 tegra_uart_read(tup, UART_IER);
1296 tegra_uart_write(tup, 0, UART_IER);
1297 tegra_uart_read(tup, UART_IER);
1300 lcr = tup->lcr_shadow;
1348 tegra_uart_write(tup, lcr, UART_LCR);
1349 tup->lcr_shadow = lcr;
1350 tup->symb_bit = symb_bit;
1357 ret = tegra_set_baudrate(tup, baud);
1359 dev_err(tup->uport.dev, "Failed to set baud rate\n");
1368 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN;
1369 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1370 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1372 if (tup->rts_active)
1373 set_rts(tup, true);
1375 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN;
1376 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1377 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1384 tegra_uart_read(tup, UART_IER);
1387 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1388 tegra_uart_read(tup, UART_IER);
1390 tup->uport.ignore_status_mask = 0;
1393 tup->uport.ignore_status_mask |= UART_LSR_DR;
1395 tup->uport.ignore_status_mask |= UART_LSR_BI;
1432 struct tegra_uart_port *tup)
1447 tup->uport.line = port;
1449 tup->enable_modem_interrupt = of_property_read_bool(np,
1454 tup->use_rx_pio = true;
1459 tup->use_tx_pio = true;
1465 tup->n_adjustable_baud_rates = n_entries / 3;
1466 tup->baud_tolerance =
1467 devm_kzalloc(&pdev->dev, (tup->n_adjustable_baud_rates) *
1468 sizeof(*tup->baud_tolerance), GFP_KERNEL);
1469 if (!tup->baud_tolerance)
1478 tup->baud_tolerance[index].lower_range_baud =
1485 tup->baud_tolerance[index].upper_range_baud =
1492 tup->baud_tolerance[index].tolerance =
1496 tup->n_adjustable_baud_rates = 0;
1566 struct tegra_uart_port *tup;
1580 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL);
1581 if (!tup) {
1582 dev_err(&pdev->dev, "Failed to allocate memory for tup\n");
1586 ret = tegra_uart_parse_dt(pdev, tup);
1590 u = &tup->uport;
1595 tup->cdata = cdata;
1597 platform_set_drvdata(pdev, tup);
1609 tup->uart_clk = devm_clk_get(&pdev->dev, NULL);
1610 if (IS_ERR(tup->uart_clk)) {
1612 return PTR_ERR(tup->uart_clk);
1615 tup->rst = devm_reset_control_get_exclusive(&pdev->dev, "serial");
1616 if (IS_ERR(tup->rst)) {
1618 return PTR_ERR(tup->rst);
1637 struct tegra_uart_port *tup = platform_get_drvdata(pdev);
1638 struct uart_port *u = &tup->uport;
1647 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1648 struct uart_port *u = &tup->uport;
1655 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1656 struct uart_port *u = &tup->uport;