Lines Matching refs:port
110 /* NOTE: earlycon port will have NULL here */
149 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
201 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
206 port->se.base = uport->membase;
238 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
244 port->loopback = RX_TX_CTS_RTS_SORTED;
258 struct qcom_geni_serial_port *port;
264 port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line];
265 return port;
272 struct qcom_geni_serial_port *port;
279 port = to_dev_port(uport, uport);
280 baud = port->baud;
283 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
472 struct qcom_geni_serial_port *port;
480 port = get_port_from_line(co->index, true);
481 if (IS_ERR(port))
484 uport = &port->uport;
494 geni_se_cancel_m_cmd(&port->se);
497 geni_se_abort_m_cmd(&port->se);
504 } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) {
520 if (port->tx_remaining)
521 qcom_geni_serial_setup_tx(uport, port->tx_remaining);
532 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
534 tport = &uport->state->port;
548 if (port->brk && buf[c] == 0) {
549 port->brk = false;
575 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
576 u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE;
580 tport = &uport->state->port;
581 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words);
585 ret = tty_insert_flip_string(tport, port->rx_fifo, bytes);
619 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
630 geni_se_cancel_m_cmd(&port->se);
633 geni_se_abort_m_cmd(&port->se);
645 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
651 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
666 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
682 geni_se_cancel_s_cmd(&port->se);
707 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
722 port->handle_rx(uport, total_bytes, drop);
728 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
743 pending = port->tx_remaining;
753 avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
761 if (!port->tx_remaining) {
763 port->tx_remaining = pending;
790 port->tx_remaining -= tx_bytes;
804 if (!port->tx_remaining) {
824 struct tty_port *tport = &uport->state->port;
825 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
857 port->brk = true;
870 static int setup_fifos(struct qcom_geni_serial_port *port)
873 u32 old_rx_fifo_depth = port->rx_fifo_depth;
875 uport = &port->uport;
876 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
877 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
878 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
880 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
882 if (port->rx_fifo && (old_rx_fifo_depth != port->rx_fifo_depth) && port->rx_fifo_depth) {
883 port->rx_fifo = devm_krealloc(uport->dev, port->rx_fifo,
884 port->rx_fifo_depth * sizeof(u32),
886 if (!port->rx_fifo)
901 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
907 proto = geni_se_read_proto(&port->se);
915 ret = setup_fifos(port);
922 if (port->rx_tx_swap) {
926 if (port->cts_rts_swap) {
931 if (port->rx_tx_swap || port->cts_rts_swap)
940 geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
942 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);
943 geni_se_select_mode(&port->se, GENI_SE_FIFO);
944 port->setup = true;
952 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
954 if (!port->setup) {
1005 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1013 port->baud = baud;
1017 ver = geni_se_get_qup_hw_version(&port->se);
1026 port->clk_rate = clk_rate;
1037 port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core;
1038 port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud);
1039 geni_icc_set_bw(&port->se);
1101 writel(port->loopback,
1125 struct qcom_geni_serial_port *port;
1135 port = get_port_from_line(co->index, true);
1136 if (IS_ERR(port)) {
1138 return PTR_ERR(port);
1141 uport = &port->uport;
1146 if (!port->setup) {
1163 __qcom_geni_serial_console_write(&dev->port, s, n);
1171 struct uart_port *uport = &dev->port;
1201 struct uart_port *uport = &dev->port;
1302 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1309 geni_icc_enable(&port->se);
1310 if (port->clk_rate)
1311 dev_pm_opp_set_rate(uport->dev, port->clk_rate);
1312 geni_se_resources_on(&port->se);
1315 geni_se_resources_off(&port->se);
1317 geni_icc_disable(&port->se);
1361 struct qcom_geni_serial_port *port;
1379 port = get_port_from_line(line, console);
1380 if (IS_ERR(port)) {
1382 return PTR_ERR(port);
1385 uport = &port->uport;
1386 /* Don't allow 2 drivers to access the same port */
1391 port->se.dev = &pdev->dev;
1392 port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1393 port->se.clk = devm_clk_get(&pdev->dev, "se");
1394 if (IS_ERR(port->se.clk)) {
1395 ret = PTR_ERR(port->se.clk);
1405 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1406 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1407 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1410 port->rx_fifo = devm_kcalloc(uport->dev,
1411 port->rx_fifo_depth, sizeof(u32), GFP_KERNEL);
1412 if (!port->rx_fifo)
1416 ret = geni_icc_get(&port->se, NULL);
1419 port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
1420 port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
1423 ret = geni_icc_set_bw(&port->se);
1427 port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
1430 if (!port->name)
1440 port->wakeup_irq = platform_get_irq_optional(pdev, 1);
1443 port->rx_tx_swap = true;
1446 port->cts_rts_swap = true;
1448 port->se.opp_table = dev_pm_opp_set_clkname(&pdev->dev, "se");
1449 if (IS_ERR(port->se.opp_table))
1450 return PTR_ERR(port->se.opp_table);
1458 port->private_data.drv = drv;
1459 uport->private_data = &port->private_data;
1460 platform_set_drvdata(pdev, port);
1461 port->handle_rx = console ? handle_rx_console : handle_rx_uart;
1469 IRQF_TRIGGER_HIGH, port->name, uport);
1476 if (port->wakeup_irq > 0) {
1479 port->wakeup_irq);
1491 dev_pm_opp_put_clkname(port->se.opp_table);
1497 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1498 struct uart_driver *drv = port->private_data.drv;
1501 dev_pm_opp_put_clkname(port->se.opp_table);
1504 uart_remove_one_port(drv, &port->uport);
1511 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1512 struct uart_port *uport = &port->uport;
1520 geni_icc_set_tag(&port->se, 0x3);
1521 geni_icc_set_bw(&port->se);
1529 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1530 struct uart_port *uport = &port->uport;
1535 geni_icc_set_tag(&port->se, 0x7);
1536 geni_icc_set_bw(&port->se);