Lines Matching defs:uport
121 struct uart_port uport;
129 int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
147 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
148 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop);
150 static void qcom_geni_serial_stop_rx(struct uart_port *uport);
151 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop);
164 .uport = {
172 .uport = {
180 .uport = {
190 .uport = {
198 static int qcom_geni_serial_request_port(struct uart_port *uport)
200 struct platform_device *pdev = to_platform_device(uport->dev);
201 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
203 uport->membase = devm_platform_ioremap_resource(pdev, 0);
204 if (IS_ERR(uport->membase))
205 return PTR_ERR(uport->membase);
206 port->se.base = uport->membase;
210 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
213 uport->type = PORT_MSM;
214 qcom_geni_serial_request_port(uport);
218 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
223 if (uart_console(uport)) {
226 geni_ios = readl(uport->membase + SE_GENI_IOS);
234 static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
238 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
240 if (uart_console(uport))
246 if (!(mctrl & TIOCM_RTS) && !uport->suspended)
248 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
251 static const char *qcom_geni_serial_get_type(struct uart_port *uport)
268 static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
276 struct qcom_geni_private_data *private_data = uport->private_data;
279 port = to_dev_port(uport, uport);
297 reg = readl(uport->membase + offset);
306 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
310 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
312 writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
315 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
320 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
323 writel(M_GENI_CMD_ABORT, uport->membase +
326 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
329 writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
332 static void qcom_geni_serial_abort_rx(struct uart_port *uport)
336 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
337 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
339 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
340 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
345 static int qcom_geni_serial_get_char(struct uart_port *uport)
347 struct qcom_geni_private_data *private_data = uport->private_data;
353 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
354 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
356 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
357 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
359 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
377 readl(uport->membase + SE_GENI_RX_FIFOn);
387 static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
390 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
391 qcom_geni_serial_setup_tx(uport, 1);
392 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
394 writel(c, uport->membase + SE_GENI_TX_FIFOn);
395 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
396 qcom_geni_serial_poll_tx_done(uport);
401 static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch)
403 struct qcom_geni_private_data *private_data = uport->private_data;
411 uport->membase + SE_GENI_TX_FIFOn);
417 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
420 struct qcom_geni_private_data *private_data = uport->private_data;
434 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
435 qcom_geni_serial_setup_tx(uport, bytes_to_send);
446 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
450 uart_console_write(uport, s + i, chars_to_write,
452 writel(M_TX_FIFO_WATERMARK_EN, uport->membase +
461 uport->membase + SE_GENI_TX_FIFOn);
465 qcom_geni_serial_poll_tx_done(uport);
471 struct uart_port *uport;
484 uport = &port->uport;
486 locked = spin_trylock_irqsave(&uport->lock, flags);
488 spin_lock_irqsave(&uport->lock, flags);
490 geni_status = readl(uport->membase + SE_GENI_STATUS);
495 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
498 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
500 writel(M_CMD_ABORT_EN, uport->membase +
503 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
509 qcom_geni_serial_poll_tx_done(uport);
511 if (uart_circ_chars_pending(&uport->state->xmit)) {
512 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
514 uport->membase + SE_GENI_M_IRQ_EN);
518 __qcom_geni_serial_console_write(uport, s, count);
521 qcom_geni_serial_setup_tx(uport, port->tx_remaining);
524 spin_unlock_irqrestore(&uport->lock, flags);
527 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
532 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
534 tport = &uport->state->port;
539 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
547 uport->icount.rx++;
550 if (uart_handle_break(uport))
554 sysrq = uart_prepare_sysrq_char(uport, buf[c]);
565 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
572 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
575 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
580 tport = &uport->state->port;
581 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words);
587 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
591 uport->icount.rx += ret;
596 static void qcom_geni_serial_start_tx(struct uart_port *uport)
601 status = readl(uport->membase + SE_GENI_STATUS);
605 if (!qcom_geni_serial_tx_empty(uport))
608 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
611 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
612 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
615 static void qcom_geni_serial_stop_tx(struct uart_port *uport)
619 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
621 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
623 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
624 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
625 status = readl(uport->membase + SE_GENI_STATUS);
631 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
634 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
636 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
638 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
641 static void qcom_geni_serial_start_rx(struct uart_port *uport)
645 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
647 status = readl(uport->membase + SE_GENI_STATUS);
649 qcom_geni_serial_stop_rx(uport);
653 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
655 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
657 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
659 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
662 static void qcom_geni_serial_stop_rx(struct uart_port *uport)
666 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
669 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
671 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
673 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
675 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
677 status = readl(uport->membase + SE_GENI_STATUS);
683 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS,
689 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
692 qcom_geni_serial_handle_rx(uport, true);
693 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
695 status = readl(uport->membase + SE_GENI_STATUS);
697 qcom_geni_serial_abort_rx(uport);
700 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
707 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
709 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
722 port->handle_rx(uport, total_bytes, drop);
725 static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done,
728 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
729 struct circ_buf *xmit = &uport->state->xmit;
739 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
749 qcom_geni_serial_stop_tx(uport);
762 qcom_geni_serial_setup_tx(uport, pending);
765 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
768 uport->membase + SE_GENI_M_IRQ_EN);
785 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
788 uport->icount.tx += tx_bytes;
801 uport->membase + SE_GENI_M_IRQ_CLEAR);
805 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
808 uport->membase + SE_GENI_M_IRQ_EN);
812 uart_write_wakeup(uport);
821 struct uart_port *uport = dev;
824 struct tty_port *tport = &uport->state->port;
825 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
827 if (uport->suspended)
830 spin_lock_irqsave(&uport->lock, flags);
831 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
832 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
833 geni_status = readl(uport->membase + SE_GENI_STATUS);
834 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
835 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
836 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
842 uport->icount.overrun++;
847 qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN,
852 uport->icount.parity++;
856 uport->icount.brk++;
862 qcom_geni_serial_handle_rx(uport, drop_rx);
865 uart_unlock_and_check_sysrq(uport, flags);
872 struct uart_port *uport;
875 uport = &port->uport;
879 uport->fifosize =
883 port->rx_fifo = devm_krealloc(uport->dev, port->rx_fifo,
894 static void qcom_geni_serial_shutdown(struct uart_port *uport)
896 disable_irq(uport->irq);
899 static int qcom_geni_serial_port_setup(struct uart_port *uport)
901 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
909 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
913 qcom_geni_serial_stop_rx(uport);
919 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
921 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL);
932 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL);
938 if (uart_console(uport))
939 qcom_geni_serial_poll_tx_done(uport);
949 static int qcom_geni_serial_startup(struct uart_port *uport)
952 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
955 ret = qcom_geni_serial_port_setup(uport);
959 enable_irq(uport->irq);
993 static void qcom_geni_serial_set_termios(struct uart_port *uport,
1005 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1010 qcom_geni_serial_stop_rx(uport);
1012 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
1025 uport->uartclk = clk_rate;
1027 dev_pm_opp_set_rate(uport->dev, clk_rate);
1042 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
1043 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
1044 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG);
1045 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG);
1098 uart_update_timeout(uport, termios->c_cflag, baud);
1100 if (!uart_console(uport))
1102 uport->membase + SE_UART_LOOPBACK_CFG);
1103 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1104 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1105 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1106 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1107 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1108 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1109 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1110 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1111 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1113 qcom_geni_serial_start_rx(uport);
1116 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
1118 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
1124 struct uart_port *uport;
1141 uport = &port->uport;
1143 if (unlikely(!uport->membase))
1147 ret = qcom_geni_serial_port_setup(uport);
1155 return uart_set_options(uport, co, baud, parity, bits, flow);
1171 struct uart_port *uport = &dev->port;
1176 ch = qcom_geni_serial_get_char(uport);
1201 struct uart_port *uport = &dev->port;
1210 if (!uport->membase)
1213 uport->private_data = &earlycon_private_data;
1216 se.base = uport->membase;
1230 qcom_geni_serial_poll_tx_done(uport);
1231 qcom_geni_serial_abort_rx(uport);
1237 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1238 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1239 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1240 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1241 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1242 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1243 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1299 static void qcom_geni_serial_pm(struct uart_port *uport,
1302 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1311 dev_pm_opp_set_rate(uport->dev, port->clk_rate);
1316 dev_pm_opp_set_rate(uport->dev, 0);
1362 struct uart_port *uport;
1385 uport = &port->uport;
1387 if (uport->private_data)
1390 uport->dev = &pdev->dev;
1403 uport->mapbase = res->start;
1410 port->rx_fifo = devm_kcalloc(uport->dev,
1427 port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
1429 uart_console(uport) ? "console" : "uart", uport->line);
1436 uport->irq = irq;
1437 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE);
1459 uport->private_data = &port->private_data;
1463 ret = uart_add_one_port(drv, uport);
1467 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN);
1468 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr,
1469 IRQF_TRIGGER_HIGH, port->name, uport);
1471 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
1472 uart_remove_one_port(drv, uport);
1482 uart_remove_one_port(drv, uport);
1504 uart_remove_one_port(drv, &port->uport);
1512 struct uart_port *uport = &port->uport;
1513 struct qcom_geni_private_data *private_data = uport->private_data;
1519 if (uart_console(uport)) {
1523 return uart_suspend_port(private_data->drv, uport);
1530 struct uart_port *uport = &port->uport;
1531 struct qcom_geni_private_data *private_data = uport->private_data;
1533 ret = uart_resume_port(private_data->drv, uport);
1534 if (uart_console(uport)) {