Lines Matching refs:port
29 /* We'll be using StrongARM sa1100 serial port major/minor */
47 * This is the size of our serial port register set.
63 return (__raw_readl(sport->port.membase + offset));
68 __raw_writel(value, sport->port.membase + offset);
78 status = sport->port.ops->get_mctrl(&sport->port);
87 sport->port.icount.rng++;
89 sport->port.icount.dsr++;
91 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
93 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
95 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
99 * This is our per-port timeout handler, for checking the
107 if (sport->port.state) {
108 spin_lock_irqsave(&sport->port.lock, flags);
110 spin_unlock_irqrestore(&sport->port.lock, flags);
119 static void pnx8xxx_stop_tx(struct uart_port *port)
122 container_of(port, struct pnx8xxx_port, port);
136 static void pnx8xxx_start_tx(struct uart_port *port)
139 container_of(port, struct pnx8xxx_port, port);
153 static void pnx8xxx_stop_rx(struct uart_port *port)
156 container_of(port, struct pnx8xxx_port, port);
170 static void pnx8xxx_enable_ms(struct uart_port *port)
173 container_of(port, struct pnx8xxx_port, port);
187 sport->port.icount.rx++;
202 sport->port.icount.brk++;
203 if (uart_handle_break(&sport->port))
206 sport->port.icount.parity++;
208 sport->port.icount.frame++;
210 sport->port.icount.overrun++;
212 status &= sport->port.read_status_mask;
219 sport->port.sysrq = 0;
222 if (uart_handle_sysrq_char(&sport->port, ch))
225 uart_insert_char(&sport->port, status,
235 spin_unlock(&sport->port.lock);
236 tty_flip_buffer_push(&sport->port.state->port);
237 spin_lock(&sport->port.lock);
242 struct circ_buf *xmit = &sport->port.state->xmit;
244 if (sport->port.x_char) {
245 serial_out(sport, PNX8XXX_FIFO, sport->port.x_char);
246 sport->port.icount.tx++;
247 sport->port.x_char = 0;
257 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
258 pnx8xxx_stop_tx(&sport->port);
269 sport->port.icount.tx++;
275 uart_write_wakeup(&sport->port);
278 pnx8xxx_stop_tx(&sport->port);
286 spin_lock(&sport->port.lock);
301 spin_unlock(&sport->port.lock);
308 static unsigned int pnx8xxx_tx_empty(struct uart_port *port)
311 container_of(port, struct pnx8xxx_port, port);
316 static unsigned int pnx8xxx_get_mctrl(struct uart_port *port)
319 container_of(port, struct pnx8xxx_port, port);
333 static void pnx8xxx_set_mctrl(struct uart_port *port, unsigned int mctrl)
336 struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
344 static void pnx8xxx_break_ctl(struct uart_port *port, int break_state)
347 container_of(port, struct pnx8xxx_port, port);
351 spin_lock_irqsave(&sport->port.lock, flags);
358 spin_unlock_irqrestore(&sport->port.lock, flags);
361 static int pnx8xxx_startup(struct uart_port *port)
364 container_of(port, struct pnx8xxx_port, port);
370 retval = request_irq(sport->port.irq, pnx8xxx_int, 0,
389 spin_lock_irq(&sport->port.lock);
390 pnx8xxx_enable_ms(&sport->port);
391 spin_unlock_irq(&sport->port.lock);
396 static void pnx8xxx_shutdown(struct uart_port *port)
399 container_of(port, struct pnx8xxx_port, port);
429 free_irq(sport->port.irq, sport);
433 pnx8xxx_set_termios(struct uart_port *port, struct ktermios *termios,
437 container_of(port, struct pnx8xxx_port, port);
468 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
469 quot = uart_get_divisor(port, baud);
471 spin_lock_irqsave(&sport->port.lock, flags);
473 sport->port.read_status_mask = ISTAT_TO_SM(PNX8XXX_UART_INT_RXOVRN) |
477 sport->port.read_status_mask |=
481 sport->port.read_status_mask |=
487 sport->port.ignore_status_mask = 0;
489 sport->port.ignore_status_mask |=
493 sport->port.ignore_status_mask |=
500 sport->port.ignore_status_mask |=
508 sport->port.ignore_status_mask |=
514 * Update the per-port timeout.
516 uart_update_timeout(port, termios->c_cflag, baud);
546 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
547 pnx8xxx_enable_ms(&sport->port);
549 spin_unlock_irqrestore(&sport->port.lock, flags);
552 static const char *pnx8xxx_type(struct uart_port *port)
555 container_of(port, struct pnx8xxx_port, port);
557 return sport->port.type == PORT_PNX8XXX ? "PNX8XXX" : NULL;
561 * Release the memory region(s) being used by 'port'.
563 static void pnx8xxx_release_port(struct uart_port *port)
566 container_of(port, struct pnx8xxx_port, port);
568 release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
572 * Request the memory region(s) being used by 'port'.
574 static int pnx8xxx_request_port(struct uart_port *port)
577 container_of(port, struct pnx8xxx_port, port);
578 return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
583 * Configure/autoconfigure the port.
585 static void pnx8xxx_config_port(struct uart_port *port, int flags)
588 container_of(port, struct pnx8xxx_port, port);
591 pnx8xxx_request_port(&sport->port) == 0)
592 sport->port.type = PORT_PNX8XXX;
601 pnx8xxx_verify_port(struct uart_port *port, struct serial_struct *ser)
604 container_of(port, struct pnx8xxx_port, port);
609 if (sport->port.irq != ser->irq)
613 if (sport->port.uartclk / 16 != ser->baud_base)
615 if ((void *)sport->port.mapbase != ser->iomem_base)
617 if (sport->port.iobase != ser->port)
660 pnx8xxx_ports[i].port.ops = &pnx8xxx_pops;
666 static void pnx8xxx_console_putchar(struct uart_port *port, int ch)
669 container_of(port, struct pnx8xxx_port, port);
694 uart_console_write(&sport->port, s, count, pnx8xxx_console_putchar);
723 * if so, search for the first available port that does have
733 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
774 return uart_suspend_port(&pnx8xxx_reg, &sport->port);
781 return uart_resume_port(&pnx8xxx_reg, &sport->port);
794 if (pnx8xxx_ports[i].port.mapbase != res->start)
797 pnx8xxx_ports[i].port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PNX8XXX_CONSOLE);
798 pnx8xxx_ports[i].port.dev = &pdev->dev;
799 uart_add_one_port(&pnx8xxx_reg, &pnx8xxx_ports[i].port);
813 uart_remove_one_port(&pnx8xxx_reg, &sport->port);
855 MODULE_DESCRIPTION("PNX8XXX SoCs serial port driver");