Lines Matching refs:R5
142 write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
172 /* Rewrite R3/R5, this time without enables masked. */
174 write_zsreg(uap, R5, regs[R5]);
564 uap->curregs[R5] |= set_bits;
565 uap->curregs[R5] &= ~clear_bits;
567 write_zsreg(uap, R5, uap->curregs[R5]);
569 set_bits, clear_bits, uap->curregs[R5]);
710 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
711 if (new_reg != uap->curregs[R5]) {
712 uap->curregs[R5] = new_reg;
713 write_zsreg(uap, R5, uap->curregs[R5]);
859 uap->curregs[R5] = Tx8 | RTS;
861 uap->curregs[R5] |= DTR;
876 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);
889 uap->curregs[R5] |= DTR;
890 write_zsreg(uap, R5, uap->curregs[R5]);
896 uap->curregs[R5] &= ~DTR;
897 write_zsreg(uap, R5, uap->curregs[R5]);
970 uap->curregs[R5] &= ~TxENABLE;
973 uap->curregs[R5] &= ~SND_BRK;
1170 uap->curregs[R5] |= DTR;
1171 write_zsreg(uap, R5, uap->curregs[R5]);
1220 uap->curregs[R5] &= ~DTR;
1221 write_zsreg(uap, R5, uap->curregs[R5]);
1967 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);