Lines Matching refs:sport
38 static inline void pic32_wait_deplete_txbuf(struct pic32_sport *sport)
41 while (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_TRMT))
45 static inline int pic32_enable_clock(struct pic32_sport *sport)
47 int ret = clk_prepare_enable(sport->clk);
52 sport->ref_clk++;
56 static inline void pic32_disable_clock(struct pic32_sport *sport)
58 sport->ref_clk--;
59 clk_disable_unprepare(sport->clk);
65 struct pic32_sport *sport = to_pic32_sport(port);
66 u32 val = pic32_uart_readl(sport, PIC32_UART_STA);
74 struct pic32_sport *sport = to_pic32_sport(port);
78 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
81 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
86 static unsigned int get_cts_state(struct pic32_sport *sport)
89 if (gpio_is_valid(sport->cts_gpio))
90 return !gpio_get_value(sport->cts_gpio);
98 struct pic32_sport *sport = to_pic32_sport(port);
101 if (!sport->hw_flow_ctrl)
103 else if (get_cts_state(sport))
118 static inline void pic32_uart_irqtxen(struct pic32_sport *sport, u8 en)
120 if (en && !tx_irq_enabled(sport)) {
121 enable_irq(sport->irq_tx);
122 tx_irq_enabled(sport) = 1;
123 } else if (!en && tx_irq_enabled(sport)) {
128 disable_irq_nosync(sport->irq_tx);
129 tx_irq_enabled(sport) = 0;
136 struct pic32_sport *sport = to_pic32_sport(port);
138 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
141 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
145 pic32_wait_deplete_txbuf(sport);
147 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
149 pic32_uart_irqtxen(sport, 0);
155 struct pic32_sport *sport = to_pic32_sport(port);
157 pic32_uart_irqtxen(sport, 1);
158 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
165 struct pic32_sport *sport = to_pic32_sport(port);
168 disable_irq(sport->irq_rx);
171 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
178 struct pic32_sport *sport = to_pic32_sport(port);
184 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
187 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
202 struct pic32_sport *sport = to_pic32_sport(port);
221 sta_reg = pic32_uart_readl(sport, PIC32_UART_STA);
225 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
237 c = pic32_uart_readl(sport, PIC32_UART_RX);
279 struct pic32_sport *sport = to_pic32_sport(port);
284 pic32_uart_writel(sport, PIC32_UART_TX, port->x_char);
308 pic32_uart_readl(sport, PIC32_UART_STA))) {
311 pic32_uart_writel(sport, PIC32_UART_TX, c);
330 pic32_uart_irqtxen(sport, 0);
366 struct pic32_sport *sport = to_pic32_sport(port);
368 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
370 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
377 struct pic32_sport *sport = to_pic32_sport(port);
380 pic32_wait_deplete_txbuf(sport);
382 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
384 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
391 struct pic32_sport *sport = to_pic32_sport(port);
398 ret = pic32_enable_clock(sport);
405 pic32_uart_writel(sport, PIC32_UART_MODE, 0);
406 pic32_uart_writel(sport, PIC32_UART_STA, 0);
412 pic32_uart_writel(sport, PIC32_UART_BRG, dflt_baud);
422 tx_irq_enabled(sport) = 0;
424 sport->irq_fault_name = kasprintf(GFP_KERNEL, "%s%d-fault",
426 sport->idx);
427 if (!sport->irq_fault_name) {
432 irq_set_status_flags(sport->irq_fault, IRQ_NOAUTOEN);
433 ret = request_irq(sport->irq_fault, pic32_uart_fault_interrupt,
434 sport->irqflags_fault, sport->irq_fault_name, port);
437 __func__, sport->irq_fault, ret,
442 sport->irq_rx_name = kasprintf(GFP_KERNEL, "%s%d-rx",
444 sport->idx);
445 if (!sport->irq_rx_name) {
450 irq_set_status_flags(sport->irq_rx, IRQ_NOAUTOEN);
451 ret = request_irq(sport->irq_rx, pic32_uart_rx_interrupt,
452 sport->irqflags_rx, sport->irq_rx_name, port);
455 __func__, sport->irq_rx, ret,
460 sport->irq_tx_name = kasprintf(GFP_KERNEL, "%s%d-tx",
462 sport->idx);
463 if (!sport->irq_tx_name) {
468 irq_set_status_flags(sport->irq_tx, IRQ_NOAUTOEN);
469 ret = request_irq(sport->irq_tx, pic32_uart_tx_interrupt,
470 sport->irqflags_tx, sport->irq_tx_name, port);
473 __func__, sport->irq_tx, ret,
481 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
485 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
491 enable_irq(sport->irq_rx);
496 kfree(sport->irq_tx_name);
497 free_irq(sport->irq_tx, port);
499 kfree(sport->irq_rx_name);
500 free_irq(sport->irq_rx, port);
502 kfree(sport->irq_fault_name);
503 free_irq(sport->irq_fault, port);
511 struct pic32_sport *sport = to_pic32_sport(port);
518 pic32_disable_clock(sport);
521 free_irq(sport->irq_fault, port);
522 free_irq(sport->irq_tx, port);
523 free_irq(sport->irq_rx, port);
531 struct pic32_sport *sport = to_pic32_sport(port);
543 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
546 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
552 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
554 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
557 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
559 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
563 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
568 if ((new->c_cflag & CRTSCTS) && sport->hw_flow_ctrl) {
570 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
572 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
574 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
578 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
580 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
582 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
595 pic32_uart_writel(sport, PIC32_UART_BRG, quot);
696 struct pic32_sport *sport = to_pic32_sport(port);
698 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
701 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
705 pic32_wait_deplete_txbuf(sport);
707 pic32_uart_writel(sport, PIC32_UART_TX, ch & 0xff);
714 struct pic32_sport *sport = pic32_sports[co->index];
715 struct uart_port *port = pic32_get_port(sport);
726 struct pic32_sport *sport;
737 sport = pic32_sports[co->index];
738 if (!sport)
740 port = pic32_get_port(sport);
742 ret = pic32_enable_clock(sport);
799 struct pic32_sport *sport;
813 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
814 if (!sport)
817 sport->idx = uart_idx;
818 sport->irq_fault = irq_of_parse_and_map(np, 0);
819 sport->irqflags_fault = IRQF_NO_THREAD;
820 sport->irq_rx = irq_of_parse_and_map(np, 1);
821 sport->irqflags_rx = IRQF_NO_THREAD;
822 sport->irq_tx = irq_of_parse_and_map(np, 2);
823 sport->irqflags_tx = IRQF_NO_THREAD;
824 sport->clk = devm_clk_get(&pdev->dev, NULL);
825 sport->cts_gpio = -EINVAL;
826 sport->dev = &pdev->dev;
831 sport->hw_flow_ctrl = false;
832 sport->cts_gpio = of_get_named_gpio(np, "cts-gpios", 0);
833 if (gpio_is_valid(sport->cts_gpio)) {
834 sport->hw_flow_ctrl = true;
836 ret = devm_gpio_request(sport->dev,
837 sport->cts_gpio, "CTS");
844 ret = gpio_direction_input(sport->cts_gpio);
851 pic32_sports[uart_idx] = sport;
852 port = &sport->port;
860 port->uartclk = clk_get_rate(sport->clk);
875 pic32_disable_clock(sport);
886 /* automatic unroll of sport and gpios */
893 struct pic32_sport *sport = to_pic32_sport(port);
896 pic32_disable_clock(sport);
898 pic32_sports[sport->idx] = NULL;
900 /* automatic unroll of sport and gpios */