Lines Matching refs:up
171 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
173 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
175 offset <<= up->port.regshift;
176 return readw(up->port.membase + offset);
179 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
181 offset <<= up->port.regshift;
182 writew(value, up->port.membase + offset);
185 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
187 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
188 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
190 serial_out(up, UART_FCR, 0);
194 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
196 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
201 return pdata->get_context_loss_count(up->dev);
205 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
207 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
212 pdata->enable_wakeup(up->dev, enable);
275 struct uart_omap_port *up = to_uart_omap_port(port);
277 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
279 pm_runtime_get_sync(up->dev);
280 up->ier |= UART_IER_MSI;
281 serial_out(up, UART_IER, up->ier);
282 pm_runtime_mark_last_busy(up->dev);
283 pm_runtime_put_autosuspend(up->dev);
288 struct uart_omap_port *up = to_uart_omap_port(port);
291 pm_runtime_get_sync(up->dev);
295 if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
303 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
304 serial_out(up, UART_OMAP_SCR, up->scr);
307 if (up->rts_gpiod &&
308 gpiod_get_value(up->rts_gpiod) != res) {
312 gpiod_set_value(up->rts_gpiod, res);
323 up->scr |= OMAP_UART_SCR_TX_EMPTY;
324 serial_out(up, UART_OMAP_SCR, up->scr);
329 if (up->ier & UART_IER_THRI) {
330 up->ier &= ~UART_IER_THRI;
331 serial_out(up, UART_IER, up->ier);
334 pm_runtime_mark_last_busy(up->dev);
335 pm_runtime_put_autosuspend(up->dev);
340 struct uart_omap_port *up = to_uart_omap_port(port);
342 pm_runtime_get_sync(up->dev);
343 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
344 up->port.read_status_mask &= ~UART_LSR_DR;
345 serial_out(up, UART_IER, up->ier);
346 pm_runtime_mark_last_busy(up->dev);
347 pm_runtime_put_autosuspend(up->dev);
350 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
352 struct circ_buf *xmit = &up->port.state->xmit;
355 if (up->port.x_char) {
356 serial_out(up, UART_TX, up->port.x_char);
357 up->port.icount.tx++;
358 up->port.x_char = 0;
359 if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
360 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
361 up->rs485_tx_filter_count++;
365 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
366 serial_omap_stop_tx(&up->port);
369 count = up->port.fifosize / 4;
371 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
373 up->port.icount.tx++;
374 if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
375 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
376 up->rs485_tx_filter_count++;
383 uart_write_wakeup(&up->port);
386 serial_omap_stop_tx(&up->port);
389 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
391 if (!(up->ier & UART_IER_THRI)) {
392 up->ier |= UART_IER_THRI;
393 serial_out(up, UART_IER, up->ier);
399 struct uart_omap_port *up = to_uart_omap_port(port);
402 pm_runtime_get_sync(up->dev);
407 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
408 serial_out(up, UART_OMAP_SCR, up->scr);
412 if (up->rts_gpiod && gpiod_get_value(up->rts_gpiod) != res) {
413 gpiod_set_value(up->rts_gpiod, res);
421 up->rs485_tx_filter_count = 0;
423 serial_omap_enable_ier_thri(up);
424 pm_runtime_mark_last_busy(up->dev);
425 pm_runtime_put_autosuspend(up->dev);
430 struct uart_omap_port *up = to_uart_omap_port(port);
433 pm_runtime_get_sync(up->dev);
434 spin_lock_irqsave(&up->port.lock, flags);
435 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
436 serial_out(up, UART_IER, up->ier);
437 spin_unlock_irqrestore(&up->port.lock, flags);
438 pm_runtime_mark_last_busy(up->dev);
439 pm_runtime_put_autosuspend(up->dev);
444 struct uart_omap_port *up = to_uart_omap_port(port);
447 pm_runtime_get_sync(up->dev);
448 spin_lock_irqsave(&up->port.lock, flags);
449 up->ier |= UART_IER_RLSI | UART_IER_RDI;
450 serial_out(up, UART_IER, up->ier);
451 spin_unlock_irqrestore(&up->port.lock, flags);
452 pm_runtime_mark_last_busy(up->dev);
453 pm_runtime_put_autosuspend(up->dev);
456 static unsigned int check_modem_status(struct uart_omap_port *up)
460 status = serial_in(up, UART_MSR);
461 status |= up->msr_saved_flags;
462 up->msr_saved_flags = 0;
466 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
467 up->port.state != NULL) {
469 up->port.icount.rng++;
471 up->port.icount.dsr++;
474 (&up->port, status & UART_MSR_DCD);
477 (&up->port, status & UART_MSR_CTS);
478 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
484 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
493 serial_in(up, UART_RX);
494 if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
495 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX) &&
496 up->rs485_tx_filter_count)
497 up->rs485_tx_filter_count--;
500 up->port.icount.rx++;
506 up->port.icount.brk++;
513 if (uart_handle_break(&up->port))
520 up->port.icount.parity++;
525 up->port.icount.frame++;
529 up->port.icount.overrun++;
532 if (up->port.line == up->port.cons->index) {
534 lsr |= up->lsr_break_flag;
537 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
540 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
548 ch = serial_in(up, UART_RX);
549 if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
550 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX) &&
551 up->rs485_tx_filter_count) {
552 up->rs485_tx_filter_count--;
557 up->port.icount.rx++;
559 if (uart_handle_sysrq_char(&up->port, ch))
562 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
572 struct uart_omap_port *up = dev_id;
578 spin_lock(&up->port.lock);
579 pm_runtime_get_sync(up->dev);
582 iir = serial_in(up, UART_IIR);
587 lsr = serial_in(up, UART_LSR);
594 check_modem_status(up);
597 transmit_chars(up, lsr);
601 serial_omap_rdi(up, lsr);
604 serial_omap_rlsi(up, lsr);
615 spin_unlock(&up->port.lock);
617 tty_flip_buffer_push(&up->port.state->port);
619 pm_runtime_mark_last_busy(up->dev);
620 pm_runtime_put_autosuspend(up->dev);
621 up->port_activity = jiffies;
628 struct uart_omap_port *up = to_uart_omap_port(port);
632 pm_runtime_get_sync(up->dev);
633 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
634 spin_lock_irqsave(&up->port.lock, flags);
635 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
636 spin_unlock_irqrestore(&up->port.lock, flags);
637 pm_runtime_mark_last_busy(up->dev);
638 pm_runtime_put_autosuspend(up->dev);
644 struct uart_omap_port *up = to_uart_omap_port(port);
648 pm_runtime_get_sync(up->dev);
649 status = check_modem_status(up);
650 pm_runtime_mark_last_busy(up->dev);
651 pm_runtime_put_autosuspend(up->dev);
653 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
668 struct uart_omap_port *up = to_uart_omap_port(port);
671 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
683 pm_runtime_get_sync(up->dev);
684 old_mcr = serial_in(up, UART_MCR);
687 up->mcr = old_mcr | mcr;
688 serial_out(up, UART_MCR, up->mcr);
691 lcr = serial_in(up, UART_LCR);
692 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
694 up->efr |= UART_EFR_RTS;
696 up->efr &= ~UART_EFR_RTS;
697 serial_out(up, UART_EFR, up->efr);
698 serial_out(up, UART_LCR, lcr);
700 pm_runtime_mark_last_busy(up->dev);
701 pm_runtime_put_autosuspend(up->dev);
706 struct uart_omap_port *up = to_uart_omap_port(port);
709 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
710 pm_runtime_get_sync(up->dev);
711 spin_lock_irqsave(&up->port.lock, flags);
713 up->lcr |= UART_LCR_SBC;
715 up->lcr &= ~UART_LCR_SBC;
716 serial_out(up, UART_LCR, up->lcr);
717 spin_unlock_irqrestore(&up->port.lock, flags);
718 pm_runtime_mark_last_busy(up->dev);
719 pm_runtime_put_autosuspend(up->dev);
724 struct uart_omap_port *up = to_uart_omap_port(port);
731 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
732 up->name, up);
736 /* Optional wake-up IRQ */
737 if (up->wakeirq) {
738 retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq);
740 free_irq(up->port.irq, up);
745 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
747 pm_runtime_get_sync(up->dev);
752 serial_omap_clear_fifos(up);
757 (void) serial_in(up, UART_LSR);
758 if (serial_in(up, UART_LSR) & UART_LSR_DR)
759 (void) serial_in(up, UART_RX);
760 (void) serial_in(up, UART_IIR);
761 (void) serial_in(up, UART_MSR);
766 serial_out(up, UART_LCR, UART_LCR_WLEN8);
767 spin_lock_irqsave(&up->port.lock, flags);
771 up->port.mctrl |= TIOCM_OUT2;
772 serial_omap_set_mctrl(&up->port, up->port.mctrl);
773 spin_unlock_irqrestore(&up->port.lock, flags);
775 up->msr_saved_flags = 0;
781 up->ier = UART_IER_RLSI | UART_IER_RDI;
782 serial_out(up, UART_IER, up->ier);
784 /* Enable module level wake up */
785 up->wer = OMAP_UART_WER_MOD_WKUP;
786 if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
787 up->wer |= OMAP_UART_TX_WAKEUP_EN;
789 serial_out(up, UART_OMAP_WER, up->wer);
791 pm_runtime_mark_last_busy(up->dev);
792 pm_runtime_put_autosuspend(up->dev);
793 up->port_activity = jiffies;
799 struct uart_omap_port *up = to_uart_omap_port(port);
802 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
804 pm_runtime_get_sync(up->dev);
808 up->ier = 0;
809 serial_out(up, UART_IER, 0);
811 spin_lock_irqsave(&up->port.lock, flags);
812 up->port.mctrl &= ~TIOCM_OUT2;
813 serial_omap_set_mctrl(&up->port, up->port.mctrl);
814 spin_unlock_irqrestore(&up->port.lock, flags);
819 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
820 serial_omap_clear_fifos(up);
825 if (serial_in(up, UART_LSR) & UART_LSR_DR)
826 (void) serial_in(up, UART_RX);
828 pm_runtime_mark_last_busy(up->dev);
829 pm_runtime_put_autosuspend(up->dev);
830 free_irq(up->port.irq, up);
831 dev_pm_clear_wake_irq(up->dev);
836 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
839 cpu_latency_qos_update_request(&up->pm_qos_request, up->latency);
846 struct uart_omap_port *up = to_uart_omap_port(port);
884 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
885 up->latency = up->calc_latency;
886 schedule_work(&up->qos_work);
888 up->dll = quot & 0xff;
889 up->dlh = quot >> 8;
890 up->mdr1 = UART_OMAP_MDR1_DISABLE;
892 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
899 pm_runtime_get_sync(up->dev);
900 spin_lock_irqsave(&up->port.lock, flags);
907 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
909 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
911 up->port.read_status_mask |= UART_LSR_BI;
916 up->port.ignore_status_mask = 0;
918 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
920 up->port.ignore_status_mask |= UART_LSR_BI;
926 up->port.ignore_status_mask |= UART_LSR_OE;
933 up->port.ignore_status_mask |= UART_LSR_DR;
938 up->ier &= ~UART_IER_MSI;
939 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
940 up->ier |= UART_IER_MSI;
941 serial_out(up, UART_IER, up->ier);
942 serial_out(up, UART_LCR, cval); /* reset DLAB */
943 up->lcr = cval;
944 up->scr = 0;
952 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
953 serial_out(up, UART_DLL, 0);
954 serial_out(up, UART_DLM, 0);
955 serial_out(up, UART_LCR, 0);
957 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
959 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
960 up->efr &= ~UART_EFR_SCD;
961 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
963 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
964 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
965 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
968 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
982 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
983 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
984 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
987 serial_out(up, UART_FCR, up->fcr);
988 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
990 serial_out(up, UART_OMAP_SCR, up->scr);
993 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
994 serial_out(up, UART_MCR, up->mcr);
995 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
996 serial_out(up, UART_EFR, up->efr);
997 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1001 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1002 serial_omap_mdr1_errataset(up, up->mdr1);
1004 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1006 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1007 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1009 serial_out(up, UART_LCR, 0);
1010 serial_out(up, UART_IER, 0);
1011 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1013 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
1014 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
1016 serial_out(up, UART_LCR, 0);
1017 serial_out(up, UART_IER, up->ier);
1018 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1020 serial_out(up, UART_EFR, up->efr);
1021 serial_out(up, UART_LCR, cval);
1024 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
1026 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
1028 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1029 serial_omap_mdr1_errataset(up, up->mdr1);
1031 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1034 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1037 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
1038 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
1041 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1042 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1043 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
1045 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
1047 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
1049 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
1051 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1052 up->efr |= UART_EFR_CTS;
1055 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
1058 if (up->port.flags & UPF_SOFT_FLOW) {
1060 up->efr &= OMAP_UART_SW_CLR;
1068 up->efr |= OMAP_UART_SW_RX;
1076 up->port.status |= UPSTAT_AUTOXOFF;
1077 up->efr |= OMAP_UART_SW_TX;
1087 up->mcr |= UART_MCR_XONANY;
1089 up->mcr &= ~UART_MCR_XONANY;
1091 serial_out(up, UART_MCR, up->mcr);
1092 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1093 serial_out(up, UART_EFR, up->efr);
1094 serial_out(up, UART_LCR, up->lcr);
1096 serial_omap_set_mctrl(&up->port, up->port.mctrl);
1098 spin_unlock_irqrestore(&up->port.lock, flags);
1099 pm_runtime_mark_last_busy(up->dev);
1100 pm_runtime_put_autosuspend(up->dev);
1101 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
1108 struct uart_omap_port *up = to_uart_omap_port(port);
1111 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1113 pm_runtime_get_sync(up->dev);
1114 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1115 efr = serial_in(up, UART_EFR);
1116 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1117 serial_out(up, UART_LCR, 0);
1119 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1120 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1121 serial_out(up, UART_EFR, efr);
1122 serial_out(up, UART_LCR, 0);
1124 pm_runtime_mark_last_busy(up->dev);
1125 pm_runtime_put_autosuspend(up->dev);
1141 struct uart_omap_port *up = to_uart_omap_port(port);
1143 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1144 up->port.line);
1145 up->port.type = PORT_OMAP;
1146 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1160 struct uart_omap_port *up = to_uart_omap_port(port);
1162 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1163 return up->name;
1168 static void __maybe_unused wait_for_xmitr(struct uart_omap_port *up)
1172 /* Wait up to 10ms for the character(s) to be sent. */
1174 status = serial_in(up, UART_LSR);
1177 up->lsr_break_flag = UART_LSR_BI;
1184 /* Wait up to 1s for flow control if necessary */
1185 if (up->port.flags & UPF_CONS_FLOW) {
1188 unsigned int msr = serial_in(up, UART_MSR);
1190 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1203 struct uart_omap_port *up = to_uart_omap_port(port);
1205 pm_runtime_get_sync(up->dev);
1206 wait_for_xmitr(up);
1207 serial_out(up, UART_TX, ch);
1208 pm_runtime_mark_last_busy(up->dev);
1209 pm_runtime_put_autosuspend(up->dev);
1214 struct uart_omap_port *up = to_uart_omap_port(port);
1217 pm_runtime_get_sync(up->dev);
1218 status = serial_in(up, UART_LSR);
1224 status = serial_in(up, UART_RX);
1227 pm_runtime_mark_last_busy(up->dev);
1228 pm_runtime_put_autosuspend(up->dev);
1297 struct uart_omap_port *up = to_uart_omap_port(port);
1299 wait_for_xmitr(up);
1300 serial_out(up, UART_TX, ch);
1307 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1312 pm_runtime_get_sync(up->dev);
1315 if (up->port.sysrq)
1318 locked = spin_trylock(&up->port.lock);
1320 spin_lock(&up->port.lock);
1325 ier = serial_in(up, UART_IER);
1326 serial_out(up, UART_IER, 0);
1328 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1334 wait_for_xmitr(up);
1335 serial_out(up, UART_IER, ier);
1343 if (up->msr_saved_flags)
1344 check_modem_status(up);
1346 pm_runtime_mark_last_busy(up->dev);
1347 pm_runtime_put_autosuspend(up->dev);
1349 spin_unlock(&up->port.lock);
1356 struct uart_omap_port *up;
1364 up = serial_omap_console_ports[co->index];
1369 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1382 static void serial_omap_add_console_port(struct uart_omap_port *up)
1384 serial_omap_console_ports[up->port.line] = up;
1393 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1402 struct uart_omap_port *up = to_uart_omap_port(port);
1406 pm_runtime_get_sync(up->dev);
1409 mode = up->ier;
1410 up->ier = 0;
1411 serial_out(up, UART_IER, 0);
1420 if (up->rts_gpiod) {
1425 gpiod_set_value(up->rts_gpiod, val);
1429 up->ier = mode;
1430 serial_out(up, UART_IER, up->ier);
1436 (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
1437 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
1438 serial_out(up, UART_OMAP_SCR, up->scr);
1441 pm_runtime_mark_last_busy(up->dev);
1442 pm_runtime_put_autosuspend(up->dev);
1484 struct uart_omap_port *up = dev_get_drvdata(dev);
1486 up->is_suspending = true;
1493 struct uart_omap_port *up = dev_get_drvdata(dev);
1495 up->is_suspending = false;
1500 struct uart_omap_port *up = dev_get_drvdata(dev);
1502 uart_suspend_port(&serial_omap_reg, &up->port);
1503 flush_work(&up->qos_work);
1506 serial_omap_enable_wakeup(up, true);
1508 serial_omap_enable_wakeup(up, false);
1515 struct uart_omap_port *up = dev_get_drvdata(dev);
1518 serial_omap_enable_wakeup(up, false);
1520 uart_resume_port(&serial_omap_reg, &up->port);
1529 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1534 mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
1554 dev_warn(up->dev,
1556 up->name);
1567 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1571 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1573 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1576 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1577 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1600 static int serial_omap_probe_rs485(struct uart_omap_port *up,
1603 struct serial_rs485 *rs485conf = &up->port.rs485;
1609 up->rts_gpiod = NULL;
1614 ret = uart_get_rs485_mode(&up->port);
1629 up->rts_gpiod = devm_gpiod_get_optional(dev, "rts", gflags);
1630 if (IS_ERR(up->rts_gpiod)) {
1631 ret = PTR_ERR(up->rts_gpiod);
1638 up->rts_gpiod = NULL;
1640 gpiod_set_consumer_name(up->rts_gpiod, "omap-serial");
1649 struct uart_omap_port *up;
1670 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1671 if (!up)
1679 up->dev = &pdev->dev;
1680 up->port.dev = &pdev->dev;
1681 up->port.type = PORT_OMAP;
1682 up->port.iotype = UPIO_MEM;
1683 up->port.irq = uartirq;
1684 up->port.regshift = 2;
1685 up->port.fifosize = 64;
1686 up->port.ops = &serial_omap_pops;
1687 up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_OMAP_CONSOLE);
1699 up->port.line = ret;
1701 if (up->port.line >= OMAP_MAX_HSUART_PORTS) {
1702 dev_err(&pdev->dev, "uart ID %d > MAX %d.\n", up->port.line,
1708 up->wakeirq = wakeirq;
1709 if (!up->wakeirq)
1710 dev_info(up->port.dev, "no wakeirq for uart%d\n",
1711 up->port.line);
1713 ret = serial_omap_probe_rs485(up, &pdev->dev);
1717 sprintf(up->name, "OMAP UART%d", up->port.line);
1718 up->port.mapbase = mem->start;
1719 up->port.membase = base;
1720 up->port.flags = omap_up_info->flags;
1721 up->port.uartclk = omap_up_info->uartclk;
1722 up->port.rs485_config = serial_omap_config_rs485;
1723 if (!up->port.uartclk) {
1724 up->port.uartclk = DEFAULT_CLK_SPEED;
1730 up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1731 up->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1732 cpu_latency_qos_add_request(&up->pm_qos_request, up->latency);
1733 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1735 platform_set_drvdata(pdev, up);
1739 device_init_wakeup(up->dev, true);
1749 omap_serial_fill_features_erratas(up);
1751 ui[up->port.line] = up;
1752 serial_omap_add_console_port(up);
1754 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1758 pm_runtime_mark_last_busy(up->dev);
1759 pm_runtime_put_autosuspend(up->dev);
1766 cpu_latency_qos_remove_request(&up->pm_qos_request);
1767 device_init_wakeup(up->dev, false);
1775 struct uart_omap_port *up = platform_get_drvdata(dev);
1777 pm_runtime_get_sync(up->dev);
1779 uart_remove_one_port(&serial_omap_reg, &up->port);
1781 pm_runtime_dont_use_autosuspend(up->dev);
1782 pm_runtime_put_sync(up->dev);
1783 pm_runtime_disable(up->dev);
1784 cpu_latency_qos_remove_request(&up->pm_qos_request);
1799 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1803 serial_out(up, UART_OMAP_MDR1, mdr1);
1805 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1811 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1816 dev_crit(up->dev, "Errata i202: timedout %x\n",
1817 serial_in(up, UART_LSR));
1825 static void serial_omap_restore_context(struct uart_omap_port *up)
1827 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1828 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1830 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1832 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1833 serial_out(up, UART_EFR, UART_EFR_ECB);
1834 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1835 serial_out(up, UART_IER, 0x0);
1836 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1837 serial_out(up, UART_DLL, up->dll);
1838 serial_out(up, UART_DLM, up->dlh);
1839 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1840 serial_out(up, UART_IER, up->ier);
1841 serial_out(up, UART_FCR, up->fcr);
1842 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1843 serial_out(up, UART_MCR, up->mcr);
1844 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1845 serial_out(up, UART_OMAP_SCR, up->scr);
1846 serial_out(up, UART_EFR, up->efr);
1847 serial_out(up, UART_LCR, up->lcr);
1848 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1849 serial_omap_mdr1_errataset(up, up->mdr1);
1851 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1852 serial_out(up, UART_OMAP_WER, up->wer);
1857 struct uart_omap_port *up = dev_get_drvdata(dev);
1859 if (!up)
1868 if (up->is_suspending && !console_suspend_enabled &&
1869 uart_console(&up->port))
1872 up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1874 serial_omap_enable_wakeup(up, true);
1876 up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1877 schedule_work(&up->qos_work);
1884 struct uart_omap_port *up = dev_get_drvdata(dev);
1886 int loss_cnt = serial_omap_get_context_loss_count(up);
1888 serial_omap_enable_wakeup(up, false);
1893 serial_omap_restore_context(up);
1894 } else if (up->context_loss_cnt != loss_cnt) {
1895 serial_omap_restore_context(up);
1897 up->latency = up->calc_latency;
1898 schedule_work(&up->qos_work);