Lines Matching refs:membase
164 st = readl(port->membase + UART_STAT);
186 unsigned int ctl = readl(port->membase + UART_INTR(port));
189 writel(ctl, port->membase + UART_INTR(port));
198 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
203 ctl = readl(port->membase + UART_INTR(port));
205 writel(ctl, port->membase + UART_INTR(port));
212 ctl = readl(port->membase + UART_CTRL(port));
214 writel(ctl, port->membase + UART_CTRL(port));
216 ctl = readl(port->membase + UART_INTR(port));
218 writel(ctl, port->membase + UART_INTR(port));
227 ctl = readl(port->membase + UART_CTRL(port));
232 writel(ctl, port->membase + UART_CTRL(port));
245 ch = readl(port->membase + UART_RBR(port));
259 ret = readl(port->membase + UART_STAT);
261 writel(ret, port->membase + UART_STAT);
303 status = readl(port->membase + UART_STAT);
316 writel(port->x_char, port->membase + UART_TSH(port));
328 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
335 st = readl(port->membase + UART_STAT);
350 unsigned int st = readl(port->membase + UART_STAT);
365 unsigned int st = readl(port->membase + UART_STAT);
377 unsigned int st = readl(port->membase + UART_STAT);
392 port->membase + UART_CTRL(port));
396 ret = readl(port->membase + UART_STAT);
398 writel(ret, port->membase + UART_STAT);
400 writel(CTRL_BRK_INT, port->membase + UART_CTRL(port));
402 ctl = readl(port->membase + UART_INTR(port));
404 writel(ctl, port->membase + UART_INTR(port));
447 writel(0, port->membase + UART_INTR(port));
478 brdv = readl(port->membase + UART_BRDV);
481 writel(brdv, port->membase + UART_BRDV);
483 osamp = readl(port->membase + UART_OSAMP);
485 writel(osamp, port->membase + UART_OSAMP);
565 unsigned int st = readl(port->membase + UART_STAT);
570 return readl(port->membase + UART_RBR(port));
578 st = readl(port->membase + UART_STAT);
586 writel(c, port->membase + UART_TSH(port));
619 st = readl(port->membase + UART_STAT);
625 writel(c, port->membase + UART_STD_TSH);
628 st = readl(port->membase + UART_STAT);
647 if (!device->port.membase)
663 readl_poll_timeout_atomic(port->membase + UART_STAT, val,
671 readl_poll_timeout_atomic(port->membase + UART_STAT, val,
678 writel(ch, port->membase + UART_TSH(port));
694 ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT;
695 intr = readl(port->membase + UART_INTR(port)) &
697 writel(0, port->membase + UART_CTRL(port));
698 writel(0, port->membase + UART_INTR(port));
705 writel(ier, port->membase + UART_CTRL(port));
708 ctl = intr | readl(port->membase + UART_INTR(port));
709 writel(ctl, port->membase + UART_INTR(port));
729 if (!port->mapbase || !port->membase) {
781 mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port));
782 mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port));
783 mvuart->pm_regs.ctrl = readl(port->membase + UART_CTRL(port));
784 mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port));
785 mvuart->pm_regs.stat = readl(port->membase + UART_STAT);
786 mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV);
787 mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP);
799 writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port));
800 writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port));
801 writel(mvuart->pm_regs.ctrl, port->membase + UART_CTRL(port));
802 writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port));
803 writel(mvuart->pm_regs.stat, port->membase + UART_STAT);
804 writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV);
805 writel(mvuart->pm_regs.osamp, port->membase + UART_OSAMP);
873 port->membase = devm_ioremap_resource(&pdev->dev, reg);
874 if (IS_ERR(port->membase))
875 return PTR_ERR(port->membase);
932 writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port));
934 writel(0, port->membase + UART_CTRL(port));