Lines Matching refs:port
108 /* Driver data, a structure for each UART port */
128 struct uart_port *port;
138 static struct mvebu_uart *to_mvuart(struct uart_port *port)
140 return (struct mvebu_uart *)port->private_data;
143 #define IS_EXTENDED(port) (to_mvuart(port)->data->is_ext)
145 #define UART_RBR(port) (to_mvuart(port)->data->regs.rbr)
146 #define UART_TSH(port) (to_mvuart(port)->data->regs.tsh)
147 #define UART_CTRL(port) (to_mvuart(port)->data->regs.ctrl)
148 #define UART_INTR(port) (to_mvuart(port)->data->regs.intr)
150 #define CTRL_TX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_tx_rdy_int)
151 #define CTRL_RX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_rx_rdy_int)
152 #define STAT_TX_RDY(port) (to_mvuart(port)->data->flags.stat_tx_rdy)
153 #define STAT_RX_RDY(port) (to_mvuart(port)->data->flags.stat_rx_rdy)
158 static unsigned int mvebu_uart_tx_empty(struct uart_port *port)
163 spin_lock_irqsave(&port->lock, flags);
164 st = readl(port->membase + UART_STAT);
165 spin_unlock_irqrestore(&port->lock, flags);
170 static unsigned int mvebu_uart_get_mctrl(struct uart_port *port)
175 static void mvebu_uart_set_mctrl(struct uart_port *port,
184 static void mvebu_uart_stop_tx(struct uart_port *port)
186 unsigned int ctl = readl(port->membase + UART_INTR(port));
188 ctl &= ~CTRL_TX_RDY_INT(port);
189 writel(ctl, port->membase + UART_INTR(port));
192 static void mvebu_uart_start_tx(struct uart_port *port)
195 struct circ_buf *xmit = &port->state->xmit;
197 if (IS_EXTENDED(port) && !uart_circ_empty(xmit)) {
198 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
200 port->icount.tx++;
203 ctl = readl(port->membase + UART_INTR(port));
204 ctl |= CTRL_TX_RDY_INT(port);
205 writel(ctl, port->membase + UART_INTR(port));
208 static void mvebu_uart_stop_rx(struct uart_port *port)
212 ctl = readl(port->membase + UART_CTRL(port));
214 writel(ctl, port->membase + UART_CTRL(port));
216 ctl = readl(port->membase + UART_INTR(port));
217 ctl &= ~CTRL_RX_RDY_INT(port);
218 writel(ctl, port->membase + UART_INTR(port));
221 static void mvebu_uart_break_ctl(struct uart_port *port, int brk)
226 spin_lock_irqsave(&port->lock, flags);
227 ctl = readl(port->membase + UART_CTRL(port));
232 writel(ctl, port->membase + UART_CTRL(port));
233 spin_unlock_irqrestore(&port->lock, flags);
236 static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status)
238 struct tty_port *tport = &port->state->port;
244 if (status & STAT_RX_RDY(port)) {
245 ch = readl(port->membase + UART_RBR(port));
248 port->icount.rx++;
251 port->icount.parity++;
258 if (IS_EXTENDED(port) && (status & STAT_BRK_ERR)) {
259 ret = readl(port->membase + UART_STAT);
261 writel(ret, port->membase + UART_STAT);
265 port->icount.brk++;
267 if (uart_handle_break(port))
272 port->icount.overrun++;
275 port->icount.frame++;
277 if (uart_handle_sysrq_char(port, ch))
280 if (status & port->ignore_status_mask & STAT_PAR_ERR)
281 status &= ~STAT_RX_RDY(port);
283 status &= port->read_status_mask;
288 status &= ~port->ignore_status_mask;
290 if (status & STAT_RX_RDY(port))
303 status = readl(port->membase + UART_STAT);
304 } while (status & (STAT_RX_RDY(port) | STAT_BRK_DET));
309 static void mvebu_uart_tx_chars(struct uart_port *port, unsigned int status)
311 struct circ_buf *xmit = &port->state->xmit;
315 if (port->x_char) {
316 writel(port->x_char, port->membase + UART_TSH(port));
317 port->icount.tx++;
318 port->x_char = 0;
322 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
323 mvebu_uart_stop_tx(port);
327 for (count = 0; count < port->fifosize; count++) {
328 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
330 port->icount.tx++;
335 st = readl(port->membase + UART_STAT);
341 uart_write_wakeup(port);
344 mvebu_uart_stop_tx(port);
349 struct uart_port *port = (struct uart_port *)dev_id;
350 unsigned int st = readl(port->membase + UART_STAT);
352 if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR |
354 mvebu_uart_rx_chars(port, st);
356 if (st & STAT_TX_RDY(port))
357 mvebu_uart_tx_chars(port, st);
364 struct uart_port *port = (struct uart_port *)dev_id;
365 unsigned int st = readl(port->membase + UART_STAT);
367 if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR |
369 mvebu_uart_rx_chars(port, st);
376 struct uart_port *port = (struct uart_port *)dev_id;
377 unsigned int st = readl(port->membase + UART_STAT);
379 if (st & STAT_TX_RDY(port))
380 mvebu_uart_tx_chars(port, st);
385 static int mvebu_uart_startup(struct uart_port *port)
387 struct mvebu_uart *mvuart = to_mvuart(port);
392 port->membase + UART_CTRL(port));
396 ret = readl(port->membase + UART_STAT);
398 writel(ret, port->membase + UART_STAT);
400 writel(CTRL_BRK_INT, port->membase + UART_CTRL(port));
402 ctl = readl(port->membase + UART_INTR(port));
403 ctl |= CTRL_RX_RDY_INT(port);
404 writel(ctl, port->membase + UART_INTR(port));
408 ret = devm_request_irq(port->dev, mvuart->irq[UART_IRQ_SUM],
409 mvebu_uart_isr, port->irqflags,
410 dev_name(port->dev), port);
412 dev_err(port->dev, "unable to request IRQ %d\n",
418 ret = devm_request_irq(port->dev, mvuart->irq[UART_RX_IRQ],
419 mvebu_uart_rx_isr, port->irqflags,
420 dev_name(port->dev), port);
422 dev_err(port->dev, "unable to request IRQ %d\n",
427 ret = devm_request_irq(port->dev, mvuart->irq[UART_TX_IRQ],
428 mvebu_uart_tx_isr, port->irqflags,
429 dev_name(port->dev),
430 port);
432 dev_err(port->dev, "unable to request IRQ %d\n",
434 devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ],
435 port);
443 static void mvebu_uart_shutdown(struct uart_port *port)
445 struct mvebu_uart *mvuart = to_mvuart(port);
447 writel(0, port->membase + UART_INTR(port));
450 devm_free_irq(port->dev, mvuart->irq[UART_IRQ_SUM], port);
452 devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ], port);
453 devm_free_irq(port->dev, mvuart->irq[UART_TX_IRQ], port);
457 static unsigned int mvebu_uart_baud_rate_set(struct uart_port *port, unsigned int baud)
462 if (!port->uartclk)
476 d_divisor = DIV_ROUND_CLOSEST(port->uartclk, baud * m_divisor);
478 brdv = readl(port->membase + UART_BRDV);
481 writel(brdv, port->membase + UART_BRDV);
483 osamp = readl(port->membase + UART_OSAMP);
485 writel(osamp, port->membase + UART_OSAMP);
487 return DIV_ROUND_CLOSEST(port->uartclk, d_divisor * m_divisor);
490 static void mvebu_uart_set_termios(struct uart_port *port,
497 spin_lock_irqsave(&port->lock, flags);
499 port->read_status_mask = STAT_RX_RDY(port) | STAT_OVR_ERR |
500 STAT_TX_RDY(port) | STAT_TX_FIFO_FUL;
503 port->read_status_mask |= STAT_FRM_ERR | STAT_PAR_ERR;
505 port->ignore_status_mask = 0;
507 port->ignore_status_mask |=
511 port->ignore_status_mask |= STAT_RX_RDY(port) | STAT_BRK_ERR;
520 min_baud = DIV_ROUND_UP(port->uartclk, 1023 * 16);
523 baud = uart_get_baud_rate(port, termios, old, min_baud, max_baud);
524 baud = mvebu_uart_baud_rate_set(port, baud);
541 uart_update_timeout(port, termios->c_cflag, baud);
544 spin_unlock_irqrestore(&port->lock, flags);
547 static const char *mvebu_uart_type(struct uart_port *port)
552 static void mvebu_uart_release_port(struct uart_port *port)
557 static int mvebu_uart_request_port(struct uart_port *port)
563 static int mvebu_uart_get_poll_char(struct uart_port *port)
565 unsigned int st = readl(port->membase + UART_STAT);
567 if (!(st & STAT_RX_RDY(port)))
570 return readl(port->membase + UART_RBR(port));
573 static void mvebu_uart_put_poll_char(struct uart_port *port, unsigned char c)
578 st = readl(port->membase + UART_STAT);
586 writel(c, port->membase + UART_TSH(port));
614 static void mvebu_uart_putc(struct uart_port *port, int c)
619 st = readl(port->membase + UART_STAT);
625 writel(c, port->membase + UART_STD_TSH);
628 st = readl(port->membase + UART_STAT);
640 uart_console_write(&dev->port, s, n, mvebu_uart_putc);
647 if (!device->port.membase)
659 static void wait_for_xmitr(struct uart_port *port)
663 readl_poll_timeout_atomic(port->membase + UART_STAT, val,
664 (val & STAT_TX_RDY(port)), 1, 10000);
667 static void wait_for_xmite(struct uart_port *port)
671 readl_poll_timeout_atomic(port->membase + UART_STAT, val,
675 static void mvebu_uart_console_putchar(struct uart_port *port, int ch)
677 wait_for_xmitr(port);
678 writel(ch, port->membase + UART_TSH(port));
684 struct uart_port *port = &mvebu_uart_ports[co->index];
690 locked = spin_trylock_irqsave(&port->lock, flags);
692 spin_lock_irqsave(&port->lock, flags);
694 ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT;
695 intr = readl(port->membase + UART_INTR(port)) &
696 (CTRL_RX_RDY_INT(port) | CTRL_TX_RDY_INT(port));
697 writel(0, port->membase + UART_CTRL(port));
698 writel(0, port->membase + UART_INTR(port));
700 uart_console_write(port, s, count, mvebu_uart_console_putchar);
702 wait_for_xmite(port);
705 writel(ier, port->membase + UART_CTRL(port));
708 ctl = intr | readl(port->membase + UART_INTR(port));
709 writel(ctl, port->membase + UART_INTR(port));
713 spin_unlock_irqrestore(&port->lock, flags);
718 struct uart_port *port;
727 port = &mvebu_uart_ports[co->index];
729 if (!port->mapbase || !port->membase) {
737 return uart_set_options(port, co, baud, parity, bits, flow);
777 struct uart_port *port = mvuart->port;
779 uart_suspend_port(&mvebu_uart_driver, port);
781 mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port));
782 mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port));
783 mvuart->pm_regs.ctrl = readl(port->membase + UART_CTRL(port));
784 mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port));
785 mvuart->pm_regs.stat = readl(port->membase + UART_STAT);
786 mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV);
787 mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP);
797 struct uart_port *port = mvuart->port;
799 writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port));
800 writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port));
801 writel(mvuart->pm_regs.ctrl, port->membase + UART_CTRL(port));
802 writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port));
803 writel(mvuart->pm_regs.stat, port->membase + UART_STAT);
804 writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV);
805 writel(mvuart->pm_regs.osamp, port->membase + UART_OSAMP);
807 uart_resume_port(&mvebu_uart_driver, port);
820 /* Counter to keep track of each UART port id when not using CONFIG_OF */
828 struct uart_port *port;
850 port = &mvebu_uart_ports[pdev->id];
852 spin_lock_init(&port->lock);
854 port->dev = &pdev->dev;
855 port->type = PORT_MVEBU;
856 port->ops = &mvebu_uart_ops;
857 port->regshift = 0;
859 port->fifosize = 32;
860 port->iotype = UPIO_MEM32;
861 port->flags = UPF_FIXED_PORT;
862 port->line = pdev->id;
866 * them per port (RX and TX). Instead, use the driver UART structure
869 port->irq = 0;
870 port->irqflags = 0;
871 port->mapbase = reg->start;
873 port->membase = devm_ioremap_resource(&pdev->dev, reg);
874 if (IS_ERR(port->membase))
875 return PTR_ERR(port->membase);
884 mvuart->port = port;
886 port->private_data = mvuart;
895 if (IS_EXTENDED(port)) {
901 port->uartclk = clk_get_rate(mvuart->clk);
916 * uart-sum of UART0 port.
932 writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port));
934 writel(0, port->membase + UART_CTRL(port));
936 return uart_add_one_port(&mvebu_uart_driver, port);