Lines Matching defs:msm_write
186 void msm_write(struct uart_port *port, unsigned int val, unsigned int off)
202 msm_write(port, 0x06, UART_MREG);
203 msm_write(port, 0xF1, UART_NREG);
204 msm_write(port, 0x0F, UART_DREG);
205 msm_write(port, 0x1A, UART_MNDREG);
214 msm_write(port, 0x18, UART_MREG);
215 msm_write(port, 0xF6, UART_NREG);
216 msm_write(port, 0x0F, UART_DREG);
217 msm_write(port, 0x0A, UART_MNDREG);
261 msm_write(port, val, UARTDM_DMEN);
391 msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);
399 msm_write(port, msm_port->imr, UART_IMR);
412 msm_write(port, msm_port->imr, UART_IMR);
418 msm_write(port, count, UARTDM_NCF_TX);
446 msm_write(port, val, UARTDM_DMEN);
449 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
450 msm_write(port, UART_CR_TX_ENABLE, UART_CR);
462 msm_write(port, msm_port->imr, UART_IMR);
510 msm_write(port, msm_port->imr, UART_IMR);
518 msm_write(port, val, UARTDM_DMEN);
523 msm_write(port, val, UARTDM_DMEN);
550 msm_write(port, val, UARTDM_DMEN);
555 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
640 msm_write(uart, msm_port->imr, UART_IMR);
646 msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR);
647 msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
653 msm_write(uart, val, UARTDM_DMEN);
655 msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX);
658 msm_write(uart, val, UARTDM_DMEN);
669 msm_write(uart, UART_CR_CMD_RESET_RX, UART_CR);
670 msm_write(uart, UART_CR_RX_ENABLE, UART_CR);
672 msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR);
673 msm_write(uart, 0xFFFFFF, UARTDM_DMRX);
674 msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
678 msm_write(uart, msm_port->imr, UART_IMR);
687 msm_write(port, msm_port->imr, UART_IMR);
698 msm_write(port, msm_port->imr, UART_IMR);
712 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
769 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
770 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
771 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
790 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
936 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
952 msm_write(port, 0, UART_IMR); /* disable interrupt */
956 msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR);
962 msm_write(port, val, UART_CR);
964 msm_write(port, val, UART_CR);
981 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
1003 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
1004 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
1005 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
1006 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
1007 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
1008 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
1011 msm_write(port, mr, UART_MR1);
1015 msm_write(port, 0, UARTDM_DMEN);
1026 msm_write(port, mr, UART_MR1);
1027 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
1030 msm_write(port, mr, UART_MR1);
1037 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
1039 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
1136 msm_write(port, entry->code, UART_CSR);
1150 msm_write(port, watermark, UART_IPR);
1154 msm_write(port, watermark, UART_RFWR);
1157 msm_write(port, 10, UART_TFWR);
1159 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
1163 msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR);
1169 msm_write(port, msm_port->imr, UART_IMR);
1172 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
1173 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1174 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
1217 msm_write(port, data, UART_MR1);
1246 msm_write(port, 0, UART_IMR); /* disable interrupts */
1313 msm_write(port, mr, UART_MR2);
1322 msm_write(port, mr, UART_MR1);
1461 msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR);
1465 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
1466 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1467 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE,
1490 msm_write(port, 0, UART_IMR);
1498 msm_write(port, imr, UART_IMR);
1510 msm_write(port, 0, UART_IMR);
1520 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
1527 msm_write(port, imr, UART_IMR);