Lines Matching refs:port
73 #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
78 static irqreturn_t mpc5xxx_uart_process_int(struct uart_port *port);
85 void (*fifo_init)(struct uart_port *port);
86 int (*raw_rx_rdy)(struct uart_port *port);
87 int (*raw_tx_rdy)(struct uart_port *port);
88 int (*rx_rdy)(struct uart_port *port);
89 int (*tx_rdy)(struct uart_port *port);
90 int (*tx_empty)(struct uart_port *port);
91 void (*stop_rx)(struct uart_port *port);
92 void (*start_tx)(struct uart_port *port);
93 void (*stop_tx)(struct uart_port *port);
94 void (*rx_clr_irq)(struct uart_port *port);
95 void (*tx_clr_irq)(struct uart_port *port);
96 void (*write_char)(struct uart_port *port, unsigned char c);
97 unsigned char (*read_char)(struct uart_port *port);
98 void (*cw_disable_ints)(struct uart_port *port);
99 void (*cw_restore_ints)(struct uart_port *port);
100 unsigned int (*set_baudrate)(struct uart_port *port,
103 int (*clock_alloc)(struct uart_port *port);
104 void (*clock_relse)(struct uart_port *port);
105 int (*clock)(struct uart_port *port, int enable);
109 irqreturn_t (*handle_irq)(struct uart_port *port);
110 u16 (*get_status)(struct uart_port *port);
111 u8 (*get_ipcr)(struct uart_port *port);
112 void (*command)(struct uart_port *port, u8 cmd);
113 void (*set_mode)(struct uart_port *port, u8 mr1, u8 mr2);
114 void (*set_rts)(struct uart_port *port, int state);
115 void (*enable_ms)(struct uart_port *port);
116 void (*set_sicr)(struct uart_port *port, u32 val);
117 void (*set_imr)(struct uart_port *port, u16 val);
118 u8 (*get_mr1)(struct uart_port *port);
131 static u16 mpc52xx_psc_get_status(struct uart_port *port)
133 return in_be16(&PSC(port)->mpc52xx_psc_status);
136 static u8 mpc52xx_psc_get_ipcr(struct uart_port *port)
138 return in_8(&PSC(port)->mpc52xx_psc_ipcr);
141 static void mpc52xx_psc_command(struct uart_port *port, u8 cmd)
143 out_8(&PSC(port)->command, cmd);
146 static void mpc52xx_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2)
148 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);
149 out_8(&PSC(port)->mode, mr1);
150 out_8(&PSC(port)->mode, mr2);
153 static void mpc52xx_psc_set_rts(struct uart_port *port, int state)
156 out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS);
158 out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS);
161 static void mpc52xx_psc_enable_ms(struct uart_port *port)
163 struct mpc52xx_psc __iomem *psc = PSC(port);
170 port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
171 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
174 static void mpc52xx_psc_set_sicr(struct uart_port *port, u32 val)
176 out_be32(&PSC(port)->sicr, val);
179 static void mpc52xx_psc_set_imr(struct uart_port *port, u16 val)
181 out_be16(&PSC(port)->mpc52xx_psc_imr, val);
184 static u8 mpc52xx_psc_get_mr1(struct uart_port *port)
186 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);
187 return in_8(&PSC(port)->mode);
191 #define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1))
192 static void mpc52xx_psc_fifo_init(struct uart_port *port)
194 struct mpc52xx_psc __iomem *psc = PSC(port);
195 struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port);
202 port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY;
203 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
206 static int mpc52xx_psc_raw_rx_rdy(struct uart_port *port)
208 return in_be16(&PSC(port)->mpc52xx_psc_status)
212 static int mpc52xx_psc_raw_tx_rdy(struct uart_port *port)
214 return in_be16(&PSC(port)->mpc52xx_psc_status)
219 static int mpc52xx_psc_rx_rdy(struct uart_port *port)
221 return in_be16(&PSC(port)->mpc52xx_psc_isr)
222 & port->read_status_mask
226 static int mpc52xx_psc_tx_rdy(struct uart_port *port)
228 return in_be16(&PSC(port)->mpc52xx_psc_isr)
229 & port->read_status_mask
233 static int mpc52xx_psc_tx_empty(struct uart_port *port)
235 u16 sts = in_be16(&PSC(port)->mpc52xx_psc_status);
240 static void mpc52xx_psc_start_tx(struct uart_port *port)
242 port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY;
243 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
246 static void mpc52xx_psc_stop_tx(struct uart_port *port)
248 port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY;
249 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
252 static void mpc52xx_psc_stop_rx(struct uart_port *port)
254 port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY;
255 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
258 static void mpc52xx_psc_rx_clr_irq(struct uart_port *port)
262 static void mpc52xx_psc_tx_clr_irq(struct uart_port *port)
266 static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c)
268 out_8(&PSC(port)->mpc52xx_psc_buffer_8, c);
271 static unsigned char mpc52xx_psc_read_char(struct uart_port *port)
273 return in_8(&PSC(port)->mpc52xx_psc_buffer_8);
276 static void mpc52xx_psc_cw_disable_ints(struct uart_port *port)
278 out_be16(&PSC(port)->mpc52xx_psc_imr, 0);
281 static void mpc52xx_psc_cw_restore_ints(struct uart_port *port)
283 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
286 static unsigned int mpc5200_psc_set_baudrate(struct uart_port *port,
294 baud = uart_get_baud_rate(port, new, old,
295 port->uartclk / (32 * 0xffff) + 1,
296 port->uartclk / 32);
297 divisor = (port->uartclk + 16 * baud) / (32 * baud);
300 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
304 static unsigned int mpc5200b_psc_set_baudrate(struct uart_port *port,
314 baud = uart_get_baud_rate(port, new, old,
315 port->uartclk / (32 * 0xffff) + 1,
316 port->uartclk / 4);
317 divisor = (port->uartclk + 2 * baud) / (4 * baud);
326 mpc52xx_set_divisor(PSC(port), prescaler, divisor);
330 static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np)
332 port->irqflags = 0;
333 port->irq = irq_of_parse_and_map(np, 0);
336 /* 52xx specific interrupt handler. The caller holds the port lock */
337 static irqreturn_t mpc52xx_psc_handle_irq(struct uart_port *port)
339 return mpc5xxx_uart_process_int(port);
405 #define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1))
420 static void mpc512x_psc_fifo_init(struct uart_port *port)
423 out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00);
425 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
426 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
427 out_be32(&FIFO_512x(port)->txalarm, 1);
428 out_be32(&FIFO_512x(port)->tximr, 0);
430 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
431 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
432 out_be32(&FIFO_512x(port)->rxalarm, 1);
433 out_be32(&FIFO_512x(port)->rximr, 0);
435 out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM);
436 out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM);
439 static int mpc512x_psc_raw_rx_rdy(struct uart_port *port)
441 return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
444 static int mpc512x_psc_raw_tx_rdy(struct uart_port *port)
446 return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL);
449 static int mpc512x_psc_rx_rdy(struct uart_port *port)
451 return in_be32(&FIFO_512x(port)->rxsr)
452 & in_be32(&FIFO_512x(port)->rximr)
456 static int mpc512x_psc_tx_rdy(struct uart_port *port)
458 return in_be32(&FIFO_512x(port)->txsr)
459 & in_be32(&FIFO_512x(port)->tximr)
463 static int mpc512x_psc_tx_empty(struct uart_port *port)
465 return in_be32(&FIFO_512x(port)->txsr)
469 static void mpc512x_psc_stop_rx(struct uart_port *port)
473 rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr);
475 out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr);
478 static void mpc512x_psc_start_tx(struct uart_port *port)
482 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
484 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
487 static void mpc512x_psc_stop_tx(struct uart_port *port)
491 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
493 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
496 static void mpc512x_psc_rx_clr_irq(struct uart_port *port)
498 out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr));
501 static void mpc512x_psc_tx_clr_irq(struct uart_port *port)
503 out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr));
506 static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c)
508 out_8(&FIFO_512x(port)->txdata_8, c);
511 static unsigned char mpc512x_psc_read_char(struct uart_port *port)
513 return in_8(&FIFO_512x(port)->rxdata_8);
516 static void mpc512x_psc_cw_disable_ints(struct uart_port *port)
518 port->read_status_mask =
519 in_be32(&FIFO_512x(port)->tximr) << 16 |
520 in_be32(&FIFO_512x(port)->rximr);
521 out_be32(&FIFO_512x(port)->tximr, 0);
522 out_be32(&FIFO_512x(port)->rximr, 0);
525 static void mpc512x_psc_cw_restore_ints(struct uart_port *port)
527 out_be32(&FIFO_512x(port)->tximr,
528 (port->read_status_mask >> 16) & 0x7f);
529 out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f);
532 static unsigned int mpc512x_psc_set_baudrate(struct uart_port *port,
553 baud = uart_get_baud_rate(port, new, old,
554 port->uartclk / (16 * 0xffff) + 1,
555 port->uartclk / 16);
556 divisor = (port->uartclk + 8 * baud) / (16 * baud);
559 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
635 /* 512x specific interrupt handler. The caller holds the port lock */
636 static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port)
644 /* Check if it is an interrupt for this port */
645 psc_num = (port->mapbase & 0xf00) >> 8;
648 return mpc5xxx_uart_process_int(port);
657 static int mpc512x_psc_alloc_clock(struct uart_port *port)
663 psc_num = (port->mapbase & 0xf00) >> 8;
665 clk = devm_clk_get(port->dev, "mclk");
667 dev_err(port->dev, "Failed to get MCLK!\n");
673 dev_err(port->dev, "Failed to enable MCLK!\n");
678 clk = devm_clk_get(port->dev, "ipg");
680 dev_err(port->dev, "Failed to get IPG clock!\n");
686 dev_err(port->dev, "Failed to enable IPG clock!\n");
706 static void mpc512x_psc_relse_clock(struct uart_port *port)
711 psc_num = (port->mapbase & 0xf00) >> 8;
724 static int mpc512x_psc_endis_clock(struct uart_port *port, int enable)
730 if (uart_console(port))
733 psc_num = (port->mapbase & 0xf00) >> 8;
736 dev_err(port->dev, "Failed to get PSC clock entry!\n");
740 dev_dbg(port->dev, "mclk %sable\n", enable ? "en" : "dis");
744 dev_err(port->dev, "Failed to enable MCLK!\n");
752 static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np)
754 port->irqflags = IRQF_SHARED;
755 port->irq = psc_fifoc_irq;
761 #define PSC_5125(port) ((struct mpc5125_psc __iomem *)((port)->membase))
762 #define FIFO_5125(port) ((struct mpc512x_psc_fifo __iomem *)(PSC_5125(port)+1))
764 static void mpc5125_psc_fifo_init(struct uart_port *port)
767 out_8(&PSC_5125(port)->mpc52xx_psc_clock_select, 0xdd);
769 out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
770 out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
771 out_be32(&FIFO_5125(port)->txalarm, 1);
772 out_be32(&FIFO_5125(port)->tximr, 0);
774 out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
775 out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
776 out_be32(&FIFO_5125(port)->rxalarm, 1);
777 out_be32(&FIFO_5125(port)->rximr, 0);
779 out_be32(&FIFO_5125(port)->tximr, MPC512x_PSC_FIFO_ALARM);
780 out_be32(&FIFO_5125(port)->rximr, MPC512x_PSC_FIFO_ALARM);
783 static int mpc5125_psc_raw_rx_rdy(struct uart_port *port)
785 return !(in_be32(&FIFO_5125(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
788 static int mpc5125_psc_raw_tx_rdy(struct uart_port *port)
790 return !(in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_FULL);
793 static int mpc5125_psc_rx_rdy(struct uart_port *port)
795 return in_be32(&FIFO_5125(port)->rxsr) &
796 in_be32(&FIFO_5125(port)->rximr) & MPC512x_PSC_FIFO_ALARM;
799 static int mpc5125_psc_tx_rdy(struct uart_port *port)
801 return in_be32(&FIFO_5125(port)->txsr) &
802 in_be32(&FIFO_5125(port)->tximr) & MPC512x_PSC_FIFO_ALARM;
805 static int mpc5125_psc_tx_empty(struct uart_port *port)
807 return in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_EMPTY;
810 static void mpc5125_psc_stop_rx(struct uart_port *port)
814 rx_fifo_imr = in_be32(&FIFO_5125(port)->rximr);
816 out_be32(&FIFO_5125(port)->rximr, rx_fifo_imr);
819 static void mpc5125_psc_start_tx(struct uart_port *port)
823 tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr);
825 out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);
828 static void mpc5125_psc_stop_tx(struct uart_port *port)
832 tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr);
834 out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);
837 static void mpc5125_psc_rx_clr_irq(struct uart_port *port)
839 out_be32(&FIFO_5125(port)->rxisr, in_be32(&FIFO_5125(port)->rxisr));
842 static void mpc5125_psc_tx_clr_irq(struct uart_port *port)
844 out_be32(&FIFO_5125(port)->txisr, in_be32(&FIFO_5125(port)->txisr));
847 static void mpc5125_psc_write_char(struct uart_port *port, unsigned char c)
849 out_8(&FIFO_5125(port)->txdata_8, c);
852 static unsigned char mpc5125_psc_read_char(struct uart_port *port)
854 return in_8(&FIFO_5125(port)->rxdata_8);
857 static void mpc5125_psc_cw_disable_ints(struct uart_port *port)
859 port->read_status_mask =
860 in_be32(&FIFO_5125(port)->tximr) << 16 |
861 in_be32(&FIFO_5125(port)->rximr);
862 out_be32(&FIFO_5125(port)->tximr, 0);
863 out_be32(&FIFO_5125(port)->rximr, 0);
866 static void mpc5125_psc_cw_restore_ints(struct uart_port *port)
868 out_be32(&FIFO_5125(port)->tximr,
869 (port->read_status_mask >> 16) & 0x7f);
870 out_be32(&FIFO_5125(port)->rximr, port->read_status_mask & 0x7f);
882 static unsigned int mpc5125_psc_set_baudrate(struct uart_port *port,
894 baud = uart_get_baud_rate(port, new, old,
895 port->uartclk / (16 * 0xffff) + 1,
896 port->uartclk / 16);
897 divisor = (port->uartclk + 8 * baud) / (16 * baud);
900 mpc5125_set_divisor(PSC_5125(port), 0xdd, divisor);
908 static u16 mpc5125_psc_get_status(struct uart_port *port)
910 return in_be16(&PSC_5125(port)->mpc52xx_psc_status);
913 static u8 mpc5125_psc_get_ipcr(struct uart_port *port)
915 return in_8(&PSC_5125(port)->mpc52xx_psc_ipcr);
918 static void mpc5125_psc_command(struct uart_port *port, u8 cmd)
920 out_8(&PSC_5125(port)->command, cmd);
923 static void mpc5125_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2)
925 out_8(&PSC_5125(port)->mr1, mr1);
926 out_8(&PSC_5125(port)->mr2, mr2);
929 static void mpc5125_psc_set_rts(struct uart_port *port, int state)
932 out_8(&PSC_5125(port)->op1, MPC52xx_PSC_OP_RTS);
934 out_8(&PSC_5125(port)->op0, MPC52xx_PSC_OP_RTS);
937 static void mpc5125_psc_enable_ms(struct uart_port *port)
939 struct mpc5125_psc __iomem *psc = PSC_5125(port);
946 port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
947 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
950 static void mpc5125_psc_set_sicr(struct uart_port *port, u32 val)
952 out_be32(&PSC_5125(port)->sicr, val);
955 static void mpc5125_psc_set_imr(struct uart_port *port, u16 val)
957 out_be16(&PSC_5125(port)->mpc52xx_psc_imr, val);
960 static u8 mpc5125_psc_get_mr1(struct uart_port *port)
962 return in_8(&PSC_5125(port)->mr1);
1044 mpc52xx_uart_tx_empty(struct uart_port *port)
1046 return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0;
1050 mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1052 psc_ops->set_rts(port, mctrl & TIOCM_RTS);
1056 mpc52xx_uart_get_mctrl(struct uart_port *port)
1059 u8 status = psc_ops->get_ipcr(port);
1070 mpc52xx_uart_stop_tx(struct uart_port *port)
1072 /* port->lock taken by caller */
1073 psc_ops->stop_tx(port);
1077 mpc52xx_uart_start_tx(struct uart_port *port)
1079 /* port->lock taken by caller */
1080 psc_ops->start_tx(port);
1084 mpc52xx_uart_stop_rx(struct uart_port *port)
1086 /* port->lock taken by caller */
1087 psc_ops->stop_rx(port);
1091 mpc52xx_uart_enable_ms(struct uart_port *port)
1093 psc_ops->enable_ms(port);
1097 mpc52xx_uart_break_ctl(struct uart_port *port, int ctl)
1100 spin_lock_irqsave(&port->lock, flags);
1103 psc_ops->command(port, MPC52xx_PSC_START_BRK);
1105 psc_ops->command(port, MPC52xx_PSC_STOP_BRK);
1107 spin_unlock_irqrestore(&port->lock, flags);
1111 mpc52xx_uart_startup(struct uart_port *port)
1116 ret = psc_ops->clock(port, 1);
1122 ret = request_irq(port->irq, mpc52xx_uart_int,
1123 port->irqflags, "mpc52xx_psc_uart", port);
1127 /* Reset/activate the port, clear and enable interrupts */
1128 psc_ops->command(port, MPC52xx_PSC_RST_RX);
1129 psc_ops->command(port, MPC52xx_PSC_RST_TX);
1138 psc_ops->set_sicr(port, 0); /* UART mode DCD ignored */
1140 psc_ops->fifo_init(port);
1142 psc_ops->command(port, MPC52xx_PSC_TX_ENABLE);
1143 psc_ops->command(port, MPC52xx_PSC_RX_ENABLE);
1149 mpc52xx_uart_shutdown(struct uart_port *port)
1151 /* Shut down the port. Leave TX active if on a console port */
1152 psc_ops->command(port, MPC52xx_PSC_RST_RX);
1153 if (!uart_console(port))
1154 psc_ops->command(port, MPC52xx_PSC_RST_TX);
1156 port->read_status_mask = 0;
1157 psc_ops->set_imr(port, port->read_status_mask);
1160 psc_ops->clock(port, 0);
1163 psc_ops->cw_disable_ints(port);
1166 free_irq(port->irq, port);
1170 mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
1218 spin_lock_irqsave(&port->lock, flags);
1226 /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */
1227 while (!mpc52xx_uart_tx_empty(port) && --j)
1236 psc_ops->command(port, MPC52xx_PSC_RST_RX);
1237 psc_ops->command(port, MPC52xx_PSC_RST_TX);
1240 psc_ops->set_mode(port, mr1, mr2);
1241 baud = psc_ops->set_baudrate(port, new, old);
1243 /* Update the per-port timeout */
1244 uart_update_timeout(port, new->c_cflag, baud);
1246 if (UART_ENABLE_MS(port, new->c_cflag))
1247 mpc52xx_uart_enable_ms(port);
1250 psc_ops->command(port, MPC52xx_PSC_TX_ENABLE);
1251 psc_ops->command(port, MPC52xx_PSC_RX_ENABLE);
1254 spin_unlock_irqrestore(&port->lock, flags);
1258 mpc52xx_uart_type(struct uart_port *port)
1264 return port->type == PORT_MPC52xx ? "MPC5xxx PSC" : NULL;
1268 mpc52xx_uart_release_port(struct uart_port *port)
1271 psc_ops->clock_relse(port);
1274 if (port->flags & UPF_IOREMAP) {
1275 iounmap(port->membase);
1276 port->membase = NULL;
1279 release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
1283 mpc52xx_uart_request_port(struct uart_port *port)
1287 if (port->flags & UPF_IOREMAP) /* Need to remap ? */
1288 port->membase = ioremap(port->mapbase,
1291 if (!port->membase)
1294 err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc),
1301 err = psc_ops->clock_alloc(port);
1309 release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
1311 if (port->flags & UPF_IOREMAP) {
1312 iounmap(port->membase);
1313 port->membase = NULL;
1319 mpc52xx_uart_config_port(struct uart_port *port, int flags)
1322 && (mpc52xx_uart_request_port(port) == 0))
1323 port->type = PORT_MPC52xx;
1327 mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1332 if ((ser->irq != port->irq) ||
1334 (ser->baud_base != port->uartclk) ||
1335 (ser->iomem_base != (void *)port->mapbase) ||
1369 mpc52xx_uart_int_rx_chars(struct uart_port *port)
1371 struct tty_port *tport = &port->state->port;
1376 while (psc_ops->raw_rx_rdy(port)) {
1378 ch = psc_ops->read_char(port);
1381 if (uart_handle_sysrq_char(port, ch))
1387 port->icount.rx++;
1389 status = psc_ops->get_status(port);
1397 uart_handle_break(port);
1398 port->icount.brk++;
1401 port->icount.parity++;
1405 port->icount.frame++;
1409 psc_ops->command(port, MPC52xx_PSC_RST_ERR_STAT);
1420 port->icount.overrun++;
1424 spin_unlock(&port->lock);
1426 spin_lock(&port->lock);
1428 return psc_ops->raw_rx_rdy(port);
1432 mpc52xx_uart_int_tx_chars(struct uart_port *port)
1434 struct circ_buf *xmit = &port->state->xmit;
1437 if (port->x_char) {
1438 psc_ops->write_char(port, port->x_char);
1439 port->icount.tx++;
1440 port->x_char = 0;
1445 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
1446 mpc52xx_uart_stop_tx(port);
1451 while (psc_ops->raw_tx_rdy(port)) {
1452 psc_ops->write_char(port, xmit->buf[xmit->tail]);
1454 port->icount.tx++;
1461 uart_write_wakeup(port);
1465 mpc52xx_uart_stop_tx(port);
1473 mpc5xxx_uart_process_int(struct uart_port *port)
1484 psc_ops->rx_clr_irq(port);
1485 if (psc_ops->rx_rdy(port))
1486 keepgoing |= mpc52xx_uart_int_rx_chars(port);
1488 psc_ops->tx_clr_irq(port);
1489 if (psc_ops->tx_rdy(port))
1490 keepgoing |= mpc52xx_uart_int_tx_chars(port);
1492 status = psc_ops->get_ipcr(port);
1494 uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD));
1497 uart_handle_cts_change(port, !(status & MPC52xx_PSC_CTS));
1511 struct uart_port *port = dev_id;
1514 spin_lock(&port->lock);
1516 ret = psc_ops->handle_irq(port);
1518 spin_unlock(&port->lock);
1530 mpc52xx_console_get_options(struct uart_port *port,
1535 pr_debug("mpc52xx_console_get_options(port=%p)\n", port);
1538 mr1 = psc_ops->get_mr1(port);
1568 struct uart_port *port = &mpc52xx_uart_ports[co->index];
1572 psc_ops->cw_disable_ints(port);
1576 while (!mpc52xx_uart_tx_empty(port) && --j)
1583 psc_ops->write_char(port, '\r');
1586 psc_ops->write_char(port, *s);
1590 while (!mpc52xx_uart_tx_empty(port) && --j)
1595 psc_ops->cw_restore_ints(port);
1602 struct uart_port *port = &mpc52xx_uart_ports[co->index];
1642 /* Basic port init. Needed since we use some uart_??? func before
1644 spin_lock_init(&port->lock);
1645 port->uartclk = uartclk;
1646 port->ops = &mpc52xx_uart_ops;
1647 port->mapbase = res.start;
1648 port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc));
1649 port->irq = irq_of_parse_and_map(np, 0);
1651 if (port->membase == NULL)
1655 (void *)port->mapbase, port->membase,
1656 port->irq, port->uartclk);
1658 /* Setup the port parameters accoding to options */
1662 mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow);
1667 return uart_set_options(port, co, baud, parity, bits, flow);
1737 struct uart_port *port = NULL;
1759 /* Init the port structure */
1760 port = &mpc52xx_uart_ports[idx];
1762 spin_lock_init(&port->lock);
1763 port->uartclk = uartclk;
1764 port->fifosize = 512;
1765 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MPC52xx_CONSOLE);
1766 port->iotype = UPIO_MEM;
1767 port->flags = UPF_BOOT_AUTOCONF |
1768 (uart_console(port) ? 0 : UPF_IOREMAP);
1769 port->line = idx;
1770 port->ops = &mpc52xx_uart_ops;
1771 port->dev = &op->dev;
1778 port->mapbase = res.start;
1779 if (!port->mapbase) {
1784 psc_ops->get_irq(port, op->dev.of_node);
1785 if (port->irq == 0) {
1791 (void *)port->mapbase, port->irq, port->uartclk);
1793 /* Add the port to the uart sub-system */
1794 ret = uart_add_one_port(&mpc52xx_uart_driver, port);
1798 platform_set_drvdata(op, (void *)port);
1805 struct uart_port *port = platform_get_drvdata(op);
1807 if (port)
1808 uart_remove_one_port(&mpc52xx_uart_driver, port);
1817 struct uart_port *port = platform_get_drvdata(op);
1819 if (port)
1820 uart_suspend_port(&mpc52xx_uart_driver, port);
1828 struct uart_port *port = platform_get_drvdata(op);
1830 if (port)
1831 uart_resume_port(&mpc52xx_uart_driver, port);