Lines Matching defs:psc
60 * psc->mpc52xx_psc_imr
122 static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc,
126 out_be16(&psc->mpc52xx_psc_clock_select, prescaler);
127 out_8(&psc->ctur, divisor >> 8);
128 out_8(&psc->ctlr, divisor & 0xff);
163 struct mpc52xx_psc __iomem *psc = PSC(port);
166 in_8(&psc->mpc52xx_psc_ipcr);
168 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
171 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
194 struct mpc52xx_psc __iomem *psc = PSC(port);
203 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
574 "fsl,mpc5121-psc-fifo");
873 static inline void mpc5125_set_divisor(struct mpc5125_psc __iomem *psc,
877 out_8(&psc->mpc52xx_psc_clock_select, prescaler);
878 out_8(&psc->ctur, divisor >> 8);
879 out_8(&psc->ctlr, divisor & 0xff);
939 struct mpc5125_psc __iomem *psc = PSC_5125(port);
942 in_8(&psc->mpc52xx_psc_ipcr);
944 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
947 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
1654 pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n",
1719 { .compatible = "fsl,mpc5200b-psc-uart", .data = &mpc5200b_psc_ops, },
1720 { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1722 { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1727 { .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, },
1728 { .compatible = "fsl,mpc5125-psc-uart", .data = &mpc5125_psc_ops, },
1750 /* set the uart clock to the input clock of the psc, the different
1790 dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n",
1889 .name = "mpc52xx-psc-uart",