Lines Matching defs:PSC
3 * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs.
73 #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
81 /* PSC fifo operations for isolating differences between 52xx and 512x */
133 return in_be16(&PSC(port)->mpc52xx_psc_status);
138 return in_8(&PSC(port)->mpc52xx_psc_ipcr);
143 out_8(&PSC(port)->command, cmd);
148 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);
149 out_8(&PSC(port)->mode, mr1);
150 out_8(&PSC(port)->mode, mr2);
156 out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS);
158 out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS);
163 struct mpc52xx_psc __iomem *psc = PSC(port);
176 out_be32(&PSC(port)->sicr, val);
181 out_be16(&PSC(port)->mpc52xx_psc_imr, val);
186 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);
187 return in_8(&PSC(port)->mode);
191 #define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1))
194 struct mpc52xx_psc __iomem *psc = PSC(port);
208 return in_be16(&PSC(port)->mpc52xx_psc_status)
214 return in_be16(&PSC(port)->mpc52xx_psc_status)
221 return in_be16(&PSC(port)->mpc52xx_psc_isr)
228 return in_be16(&PSC(port)->mpc52xx_psc_isr)
235 u16 sts = in_be16(&PSC(port)->mpc52xx_psc_status);
243 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
249 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
255 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
268 out_8(&PSC(port)->mpc52xx_psc_buffer_8, c);
273 return in_8(&PSC(port)->mpc52xx_psc_buffer_8);
278 out_be16(&PSC(port)->mpc52xx_psc_imr, 0);
283 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
300 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
326 mpc52xx_set_divisor(PSC(port), prescaler, divisor);
405 #define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1))
407 /* PSC FIFO Controller for mpc512x */
423 out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00);
548 * Chapter 4.1 PSC in UART Mode.
559 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
563 /* Init PSC FIFO Controller */
641 /* Read pending PSC FIFOC interrupts */
736 dev_err(port->dev, "Failed to get PSC clock entry!\n");
905 * MPC5125 have compatible PSC FIFO Controller.
1264 return port->type == PORT_MPC52xx ? "MPC5xxx PSC" : NULL;
1617 pr_debug("PSC%x out of range\n", co->index);
1622 pr_debug("PSC%x not found in device tree\n", co->index);
1632 pr_debug("Could not get resources for PSC%x\n", co->index);
1780 dev_dbg(&op->dev, "Could not allocate resources for PSC\n");
1842 /* Find the first free PSC number */
1863 /* Assign index to each PSC in device tree */
1904 printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n");
1916 * Map the PSC FIFO Controller and init if on MPC512x.
1955 MODULE_DESCRIPTION("Freescale MPC52xx PSC UART");