Lines Matching refs:membase
67 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE,
68 port->membase + MLB_USIO_REG_FCR);
69 writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_TBIE,
70 port->membase + MLB_USIO_REG_SCR);
78 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE,
79 port->membase + MLB_USIO_REG_FCR);
80 writeb(readb(port->membase + MLB_USIO_REG_SCR) &
82 port->membase + MLB_USIO_REG_SCR);
85 writew(port->x_char, port->membase + MLB_USIO_REG_DR);
96 (readw(port->membase + MLB_USIO_REG_FBYTE) & 0xff);
99 writew(xmit->buf[xmit->tail], port->membase + MLB_USIO_REG_DR);
108 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FDRQ,
109 port->membase + MLB_USIO_REG_FCR);
111 writeb(readb(port->membase + MLB_USIO_REG_SCR) | MLB_USIO_SCR_TBIE,
112 port->membase + MLB_USIO_REG_SCR);
123 u16 fcr = readw(port->membase + MLB_USIO_REG_FCR);
125 writew(fcr | MLB_USIO_FCR_FTIE, port->membase + MLB_USIO_REG_FCR);
129 writeb(readb(port->membase + MLB_USIO_REG_SCR) | MLB_USIO_SCR_TBIE,
130 port->membase + MLB_USIO_REG_SCR);
132 if (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI)
138 writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_RIE,
139 port->membase + MLB_USIO_REG_SCR);
144 writeb(readb(port->membase + MLB_USIO_REG_SCR) |
146 port->membase + MLB_USIO_REG_SCR);
158 status = readb(port->membase + MLB_USIO_REG_SSR);
165 ch = readw(port->membase + MLB_USIO_REG_DR);
195 writeb(readb(port->membase + MLB_USIO_REG_SSR) |
197 port->membase + MLB_USIO_REG_SSR);
199 max_count = readw(port->membase + MLB_USIO_REG_FBYTE) >> 8;
200 writew(readw(port->membase + MLB_USIO_REG_FCR) |
202 port->membase + MLB_USIO_REG_FCR);
224 if (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI)
233 return (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI) ?
269 escr = readb(port->membase + MLB_USIO_REG_ESCR);
273 writeb(0, port->membase + MLB_USIO_REG_SCR);
274 writeb(escr, port->membase + MLB_USIO_REG_ESCR);
275 writeb(MLB_USIO_SCR_UPCL, port->membase + MLB_USIO_REG_SCR);
276 writeb(MLB_USIO_SSR_REC, port->membase + MLB_USIO_REG_SSR);
277 writew(0, port->membase + MLB_USIO_REG_FCR);
279 port->membase + MLB_USIO_REG_FCR);
281 port->membase + MLB_USIO_REG_FCR);
282 writew(0, port->membase + MLB_USIO_REG_FBYTE);
283 writew(BIT(12), port->membase + MLB_USIO_REG_FBYTE);
286 MLB_USIO_SCR_RXE, port->membase + MLB_USIO_REG_SCR);
356 writeb(0, port->membase + MLB_USIO_REG_SCR);
357 writeb(MLB_USIO_SCR_UPCL, port->membase + MLB_USIO_REG_SCR);
358 writeb(MLB_USIO_SSR_REC, port->membase + MLB_USIO_REG_SSR);
359 writew(0, port->membase + MLB_USIO_REG_FCR);
360 writeb(smr, port->membase + MLB_USIO_REG_SMR);
361 writeb(escr, port->membase + MLB_USIO_REG_ESCR);
362 writew(quot, port->membase + MLB_USIO_REG_BGR);
363 writew(0, port->membase + MLB_USIO_REG_FCR);
366 port->membase + MLB_USIO_REG_FCR);
367 writew(0, port->membase + MLB_USIO_REG_FBYTE);
368 writew(BIT(12), port->membase + MLB_USIO_REG_FBYTE);
370 MLB_USIO_SCR_TXE, port->membase + MLB_USIO_REG_SCR);
405 while (!(readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TDRE))
408 writew(c, port->membase + MLB_USIO_REG_DR);
431 if (!port->membase)
475 if (!device->port.membase)
524 port->membase = devm_ioremap(&pdev->dev, res->start,