Lines Matching refs:val
94 u32 val;
96 val = readl(port->membase + AML_UART_STATUS);
97 val &= (AML_UART_TX_EMPTY | AML_UART_XMIT_BUSY);
98 return (val == AML_UART_TX_EMPTY) ? TIOCSER_TEMT : 0;
103 u32 val;
105 val = readl(port->membase + AML_UART_CONTROL);
106 val &= ~AML_UART_TX_INT_EN;
107 writel(val, port->membase + AML_UART_CONTROL);
112 u32 val;
114 val = readl(port->membase + AML_UART_CONTROL);
115 val &= ~AML_UART_RX_EN;
116 writel(val, port->membase + AML_UART_CONTROL);
122 u32 val;
128 val = readl(port->membase + AML_UART_CONTROL);
129 val &= ~AML_UART_RX_EN;
130 val &= ~(AML_UART_RX_INT_EN | AML_UART_TX_INT_EN);
131 writel(val, port->membase + AML_UART_CONTROL);
140 u32 val;
165 val = readl(port->membase + AML_UART_CONTROL);
166 val |= AML_UART_TX_INT_EN;
167 writel(val, port->membase + AML_UART_CONTROL);
268 u32 val;
270 val = readl(port->membase + AML_UART_CONTROL);
271 val |= (AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLEAR_ERR);
272 writel(val, port->membase + AML_UART_CONTROL);
274 val &= ~(AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLEAR_ERR);
275 writel(val, port->membase + AML_UART_CONTROL);
281 u32 val;
286 val = readl(port->membase + AML_UART_CONTROL);
287 val |= AML_UART_CLEAR_ERR;
288 writel(val, port->membase + AML_UART_CONTROL);
289 val &= ~AML_UART_CLEAR_ERR;
290 writel(val, port->membase + AML_UART_CONTROL);
292 val |= (AML_UART_RX_EN | AML_UART_TX_EN);
293 writel(val, port->membase + AML_UART_CONTROL);
295 val |= (AML_UART_RX_INT_EN | AML_UART_TX_INT_EN);
296 writel(val, port->membase + AML_UART_CONTROL);
298 val = (AML_UART_RECV_IRQ(1) | AML_UART_XMIT_IRQ(port->fifosize / 2));
299 writel(val, port->membase + AML_UART_MISC);
311 u32 val;
317 val = ((port->uartclk / 3) / baud) - 1;
318 val |= AML_UART_BAUD_XTAL;
320 val = ((port->uartclk * 10 / (baud * 4) + 5) / 10) - 1;
322 val |= AML_UART_BAUD_USE;
323 writel(val, port->membase + AML_UART_REG5);
332 u32 val;
339 val = readl(port->membase + AML_UART_CONTROL);
341 val &= ~AML_UART_DATA_LEN_MASK;
344 val |= AML_UART_DATA_LEN_8BIT;
347 val |= AML_UART_DATA_LEN_7BIT;
350 val |= AML_UART_DATA_LEN_6BIT;
353 val |= AML_UART_DATA_LEN_5BIT;
358 val |= AML_UART_PARITY_EN;
360 val &= ~AML_UART_PARITY_EN;
363 val |= AML_UART_PARITY_TYPE;
365 val &= ~AML_UART_PARITY_TYPE;
367 val &= ~AML_UART_STOP_BIT_LEN_MASK;
369 val |= AML_UART_STOP_BIT_2SB;
371 val |= AML_UART_STOP_BIT_1SB;
375 val &= ~AML_UART_TWO_WIRE_EN;
379 val |= AML_UART_TWO_WIRE_EN;
382 writel(val, port->membase + AML_UART_CONTROL);
528 u32 val;
530 val = readl(port->membase + AML_UART_CONTROL);
531 val |= AML_UART_TX_EN;
532 writel(val, port->membase + AML_UART_CONTROL);
550 u32 val, tmp;
562 val = readl(port->membase + AML_UART_CONTROL);
563 tmp = val & ~(AML_UART_TX_INT_EN | AML_UART_RX_INT_EN);
567 writel(val, port->membase + AML_UART_CONTROL);