Lines Matching refs:membase
96 val = readl(port->membase + AML_UART_STATUS);
105 val = readl(port->membase + AML_UART_CONTROL);
107 writel(val, port->membase + AML_UART_CONTROL);
114 val = readl(port->membase + AML_UART_CONTROL);
116 writel(val, port->membase + AML_UART_CONTROL);
128 val = readl(port->membase + AML_UART_CONTROL);
131 writel(val, port->membase + AML_UART_CONTROL);
147 while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) {
149 writel(port->x_char, port->membase + AML_UART_WFIFO);
159 writel(ch, port->membase + AML_UART_WFIFO);
165 val = readl(port->membase + AML_UART_CONTROL);
167 writel(val, port->membase + AML_UART_CONTROL);
183 ostatus = status = readl(port->membase + AML_UART_STATUS);
193 mode = readl(port->membase + AML_UART_CONTROL);
195 writel(mode, port->membase + AML_UART_CONTROL);
199 writel(mode, port->membase + AML_UART_CONTROL);
208 ch = readl(port->membase + AML_UART_RFIFO);
227 } while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY));
240 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY))
243 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) {
244 if (readl(port->membase + AML_UART_CONTROL) & AML_UART_TX_INT_EN)
270 val = readl(port->membase + AML_UART_CONTROL);
272 writel(val, port->membase + AML_UART_CONTROL);
275 writel(val, port->membase + AML_UART_CONTROL);
286 val = readl(port->membase + AML_UART_CONTROL);
288 writel(val, port->membase + AML_UART_CONTROL);
290 writel(val, port->membase + AML_UART_CONTROL);
293 writel(val, port->membase + AML_UART_CONTROL);
296 writel(val, port->membase + AML_UART_CONTROL);
299 writel(val, port->membase + AML_UART_MISC);
323 writel(val, port->membase + AML_UART_REG5);
339 val = readl(port->membase + AML_UART_CONTROL);
382 writel(val, port->membase + AML_UART_CONTROL);
417 devm_iounmap(port->dev, port->membase);
418 port->membase = NULL;
430 port->membase = devm_ioremap(port->dev, port->mapbase,
432 if (!port->membase)
459 if (readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY)
462 c = readl(port->membase + AML_UART_RFIFO);
478 ret = readl_poll_timeout_atomic(port->membase + AML_UART_STATUS, reg,
488 writel(c, port->membase + AML_UART_WFIFO);
491 ret = readl_poll_timeout_atomic(port->membase + AML_UART_STATUS, reg,
530 val = readl(port->membase + AML_UART_CONTROL);
532 writel(val, port->membase + AML_UART_CONTROL);
537 if (!port->membase)
540 while (readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)
542 writel(ch, port->membase + AML_UART_WFIFO);
562 val = readl(port->membase + AML_UART_CONTROL);
564 writel(tmp, port->membase + AML_UART_CONTROL);
567 writel(val, port->membase + AML_UART_CONTROL);
598 if (!port || !port->membase)
638 if (!device->port.membase)