Lines Matching refs:membase
62 return (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXEMPTY) ?
73 sigs = (readb(port->membase + MCFUART_UIPR) & MCFUART_UIPR_CTS) ?
91 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);
93 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP0);
104 writeb(MCFUART_UCR_TXENABLE, port->membase + MCFUART_UCR);
106 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);
109 writeb(pp->imr, port->membase + MCFUART_UIMR);
119 writeb(pp->imr, port->membase + MCFUART_UIMR);
129 writeb(pp->imr, port->membase + MCFUART_UIMR);
140 writeb(MCFUART_UCR_CMDBREAKSTART, port->membase + MCFUART_UCR);
142 writeb(MCFUART_UCR_CMDBREAKSTOP, port->membase + MCFUART_UCR);
156 writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
157 writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
161 port->membase + MCFUART_UCR);
165 writeb(pp->imr, port->membase + MCFUART_UIMR);
183 writeb(pp->imr, port->membase + MCFUART_UIMR);
186 writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
187 writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
262 writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
263 writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
264 writeb(MCFUART_UCR_CMDRESETMRPTR, port->membase + MCFUART_UCR);
265 writeb(mr1, port->membase + MCFUART_UMR);
266 writeb(mr2, port->membase + MCFUART_UMR);
267 writeb((baudclk & 0xff00) >> 8, port->membase + MCFUART_UBG1);
268 writeb((baudclk & 0xff), port->membase + MCFUART_UBG2);
270 writeb((baudfr & 0x0f), port->membase + MCFUART_UFPD);
273 port->membase + MCFUART_UCSR);
275 port->membase + MCFUART_UCR);
286 while ((status = readb(port->membase + MCFUART_USR)) & MCFUART_USR_RXREADY) {
287 ch = readb(port->membase + MCFUART_URB);
293 port->membase + MCFUART_UCR);
336 writeb(port->x_char, port->membase + MCFUART_UTB);
342 while (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY) {
345 writeb(xmit->buf[xmit->tail], port->membase + MCFUART_UTB);
355 writeb(pp->imr, port->membase + MCFUART_UIMR);
359 port->membase + MCFUART_UCR);
372 isr = readb(port->membase + MCFUART_UISR) & pp->imr;
396 writeb(0, port->membase + MCFUART_UIMR);
442 mr1 = readb(port->membase + MCFUART_UMR);
443 mr2 = readb(port->membase + MCFUART_UMR);
452 writeb(mr1, port->membase + MCFUART_UMR);
453 writeb(mr2, port->membase + MCFUART_UMR);
501 port->membase = (platp[i].membase) ? platp[i].membase :
522 if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY)
525 writeb(c, port->membase + MCFUART_UTB);
527 if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY)
556 if (port->membase == 0)
626 port->membase = (platp[i].membase) ? platp[i].membase :