Lines Matching refs:port
261 struct uart_port port;
271 container_of(_port, struct max310x_one, port)
294 static u8 max310x_port_read(struct uart_port *port, u8 reg)
296 struct max310x_port *s = dev_get_drvdata(port->dev);
299 regmap_read(s->regmap, port->iobase + reg, &val);
304 static void max310x_port_write(struct uart_port *port, u8 reg, u8 val)
306 struct max310x_port *s = dev_get_drvdata(port->dev);
308 regmap_write(s->regmap, port->iobase + reg, val);
311 static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val)
313 struct max310x_port *s = dev_get_drvdata(port->dev);
315 regmap_update_bits(s->regmap, port->iobase + reg, mask, val);
380 static void max310x_power(struct uart_port *port, int on)
382 max310x_port_update(port, MAX310X_MODE1_REG,
411 static void max14830_power(struct uart_port *port, int on)
413 max310x_port_update(port, MAX310X_BRGCFG_REG,
506 static int max310x_set_baud(struct uart_port *port, int baud)
515 div = port->uartclk / baud;
534 frac = (16*(port->uartclk % F)) / F;
538 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, div >> 8);
539 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div);
540 max310x_port_write(port, MAX310X_BRGCFG_REG, frac | mode);
543 return (16*port->uartclk) / (c*(16*div + frac));
635 static void max310x_batch_write(struct uart_port *port, u8 *txbuf, unsigned int len)
637 struct max310x_one *one = to_max310x_port(port);
647 spi_sync_transfer(to_spi_device(port->dev), xfer, ARRAY_SIZE(xfer));
650 static void max310x_batch_read(struct uart_port *port, u8 *rxbuf, unsigned int len)
652 struct max310x_one *one = to_max310x_port(port);
662 spi_sync_transfer(to_spi_device(port->dev), xfer, ARRAY_SIZE(xfer));
665 static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen)
667 struct max310x_one *one = to_max310x_port(port);
670 if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) {
682 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
683 max310x_batch_read(port, one->rx_buf, rxlen);
685 port->icount.rx += rxlen;
687 sts &= port->read_status_mask;
690 dev_warn_ratelimited(port->dev, "Hardware RX FIFO overrun\n");
691 port->icount.overrun++;
695 uart_insert_char(port, sts, 0, one->rx_buf[i], flag);
702 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT,
706 if (unlikely(rxlen >= port->fifosize)) {
707 dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n");
708 port->icount.buf_overrun++;
710 rxlen = port->fifosize;
714 ch = max310x_port_read(port, MAX310X_RHR_REG);
715 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
720 port->icount.rx++;
725 port->icount.brk++;
726 if (uart_handle_break(port))
729 port->icount.parity++;
731 port->icount.frame++;
733 port->icount.overrun++;
735 sts &= port->read_status_mask;
746 if (uart_handle_sysrq_char(port, ch))
749 if (sts & port->ignore_status_mask)
752 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag);
756 tty_flip_buffer_push(&port->state->port);
759 static void max310x_handle_tx(struct uart_port *port)
761 struct circ_buf *xmit = &port->state->xmit;
764 if (unlikely(port->x_char)) {
765 max310x_port_write(port, MAX310X_THR_REG, port->x_char);
766 port->icount.tx++;
767 port->x_char = 0;
771 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
779 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
780 txlen = port->fifosize - txlen;
786 max310x_batch_write(port, xmit->buf + xmit->tail, until_end);
787 max310x_batch_write(port, xmit->buf, to_send - until_end);
789 max310x_batch_write(port, xmit->buf + xmit->tail, to_send);
793 port->icount.tx += to_send;
798 uart_write_wakeup(port);
801 static void max310x_start_tx(struct uart_port *port)
803 struct max310x_one *one = to_max310x_port(port);
810 struct uart_port *port = &s->p[portno].port;
817 ists = max310x_port_read(port, MAX310X_IRQSTS_REG);
818 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG);
825 lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
826 uart_handle_cts_change(port,
830 max310x_handle_rx(port, rxlen);
832 max310x_start_tx(port);
866 max310x_handle_tx(&one->port);
869 static unsigned int max310x_tx_empty(struct uart_port *port)
871 u8 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
876 static unsigned int max310x_get_mctrl(struct uart_port *port)
888 max310x_port_update(&one->port, MAX310X_MODE2_REG,
890 (one->port.mctrl & TIOCM_LOOP) ?
894 static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl)
896 struct max310x_one *one = to_max310x_port(port);
901 static void max310x_break_ctl(struct uart_port *port, int break_state)
903 max310x_port_update(port, MAX310X_LCR_REG,
908 static void max310x_set_termios(struct uart_port *port,
946 max310x_port_write(port, MAX310X_LCR_REG, lcr);
949 port->read_status_mask = MAX310X_LSR_RXOVR_BIT;
951 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT |
954 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT;
957 port->ignore_status_mask = 0;
959 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT;
961 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT |
967 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]);
968 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]);
974 max310x_port_update(port, MAX310X_MODE1_REG,
979 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
983 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
991 port->status |= UPSTAT_AUTOXOFF;
995 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow);
1001 max310x_port_update(port, MAX310X_MODE1_REG,
1007 baud = uart_get_baud_rate(port, termios, old,
1008 port->uartclk / 16 / 0xffff,
1009 port->uartclk / 4);
1012 baud = max310x_set_baud(port, baud);
1015 uart_update_timeout(port, termios->c_cflag, baud);
1023 delay = (one->port.rs485.delay_rts_before_send << 4) |
1024 one->port.rs485.delay_rts_after_send;
1025 max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, delay);
1027 if (one->port.rs485.flags & SER_RS485_ENABLED) {
1030 if (!(one->port.rs485.flags & SER_RS485_RX_DURING_TX))
1034 max310x_port_update(&one->port, MAX310X_MODE1_REG,
1036 max310x_port_update(&one->port, MAX310X_MODE2_REG,
1040 static int max310x_rs485_config(struct uart_port *port,
1043 struct max310x_one *one = to_max310x_port(port);
1052 port->rs485 = *rs485;
1059 static int max310x_startup(struct uart_port *port)
1061 struct max310x_port *s = dev_get_drvdata(port->dev);
1064 s->devtype->power(port, 1);
1067 max310x_port_update(port, MAX310X_MODE1_REG,
1072 max310x_port_write(port, MAX310X_MODE2_REG, val);
1073 max310x_port_update(port, MAX310X_MODE2_REG,
1077 val = (clamp(port->rs485.delay_rts_before_send, 0U, 15U) << 4) |
1078 clamp(port->rs485.delay_rts_after_send, 0U, 15U);
1079 max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val);
1081 if (port->rs485.flags & SER_RS485_ENABLED) {
1082 max310x_port_update(port, MAX310X_MODE1_REG,
1086 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
1087 max310x_port_update(port, MAX310X_MODE2_REG,
1094 max310x_port_write(port, MAX310X_FLOWLVL_REG,
1098 max310x_port_read(port, MAX310X_IRQSTS_REG);
1102 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT);
1107 static void max310x_shutdown(struct uart_port *port)
1109 struct max310x_port *s = dev_get_drvdata(port->dev);
1112 max310x_port_write(port, MAX310X_IRQEN_REG, 0);
1114 s->devtype->power(port, 0);
1117 static const char *max310x_type(struct uart_port *port)
1119 struct max310x_port *s = dev_get_drvdata(port->dev);
1121 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL;
1124 static int max310x_request_port(struct uart_port *port)
1130 static void max310x_config_port(struct uart_port *port, int flags)
1133 port->type = PORT_MAX310X;
1136 static int max310x_verify_port(struct uart_port *port, struct serial_struct *s)
1140 if (s->irq != port->irq)
1146 static void max310x_null_void(struct uart_port *port)
1175 uart_suspend_port(&max310x_uart, &s->p[i].port);
1176 s->devtype->power(&s->p[i].port, 0);
1188 s->devtype->power(&s->p[i].port, 1);
1189 uart_resume_port(&max310x_uart, &s->p[i].port);
1202 struct uart_port *port = &s->p[offset / 4].port;
1204 val = max310x_port_read(port, MAX310X_GPIODATA_REG);
1212 struct uart_port *port = &s->p[offset / 4].port;
1214 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1221 struct uart_port *port = &s->p[offset / 4].port;
1223 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0);
1232 struct uart_port *port = &s->p[offset / 4].port;
1234 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1236 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4),
1246 struct uart_port *port = &s->p[offset / 4].port;
1250 max310x_port_update(port, MAX310X_GPIOCFG_REG,
1255 max310x_port_update(port, MAX310X_GPIOCFG_REG,
1275 /* Alloc port structure */
1278 dev_err(dev, "Error allocating port structure\n");
1324 /* Reset port */
1327 /* Clear port reset */
1330 /* Wait for port startup */
1352 /* Initialize port data */
1353 s->p[i].port.line = line;
1354 s->p[i].port.dev = dev;
1355 s->p[i].port.irq = irq;
1356 s->p[i].port.type = PORT_MAX310X;
1357 s->p[i].port.fifosize = MAX310X_FIFO_SIZE;
1358 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1359 s->p[i].port.iotype = UPIO_PORT;
1360 s->p[i].port.iobase = i * 0x20;
1361 s->p[i].port.membase = (void __iomem *)~0;
1362 s->p[i].port.uartclk = uartclk;
1363 s->p[i].port.rs485_config = max310x_rs485_config;
1364 s->p[i].port.ops = &max310x_ops;
1366 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0);
1368 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG);
1376 s->p[i].wr_header = (s->p[i].port.iobase + MAX310X_THR_REG) |
1378 s->p[i].rd_header = (s->p[i].port.iobase + MAX310X_RHR_REG);
1380 /* Register port */
1381 ret = uart_add_one_port(&max310x_uart, &s->p[i].port);
1383 s->p[i].port.dev = NULL;
1389 devtype->power(&s->p[i].port, 0);
1420 if (s->p[i].port.dev) {
1421 uart_remove_one_port(&max310x_uart, &s->p[i].port);
1422 clear_bit(s->p[i].port.line, max310x_lines);
1441 uart_remove_one_port(&max310x_uart, &s->p[i].port);
1442 clear_bit(s->p[i].port.line, max310x_lines);
1443 s->devtype->power(&s->p[i].port, 0);