Lines Matching refs:ch
35 static void neo_set_cts_flow_control(struct jsm_channel *ch)
38 ier = readb(&ch->ch_neo_uart->ier);
39 efr = readb(&ch->ch_neo_uart->efr);
41 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n");
51 writeb(0, &ch->ch_neo_uart->efr);
54 writeb(efr, &ch->ch_neo_uart->efr);
57 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
60 writeb(8, &ch->ch_neo_uart->tfifo);
61 ch->ch_t_tlevel = 8;
63 writeb(ier, &ch->ch_neo_uart->ier);
66 static void neo_set_rts_flow_control(struct jsm_channel *ch)
69 ier = readb(&ch->ch_neo_uart->ier);
70 efr = readb(&ch->ch_neo_uart->efr);
72 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting RTSFLOW\n");
83 writeb(0, &ch->ch_neo_uart->efr);
86 writeb(efr, &ch->ch_neo_uart->efr);
88 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
89 ch->ch_r_watermark = 4;
91 writeb(56, &ch->ch_neo_uart->rfifo);
92 ch->ch_r_tlevel = 56;
94 writeb(ier, &ch->ch_neo_uart->ier);
102 ch->ch_mostat |= (UART_MCR_RTS);
106 static void neo_set_ixon_flow_control(struct jsm_channel *ch)
109 ier = readb(&ch->ch_neo_uart->ier);
110 efr = readb(&ch->ch_neo_uart->efr);
112 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXON FLOW\n");
122 writeb(0, &ch->ch_neo_uart->efr);
125 writeb(efr, &ch->ch_neo_uart->efr);
127 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
128 ch->ch_r_watermark = 4;
130 writeb(32, &ch->ch_neo_uart->rfifo);
131 ch->ch_r_tlevel = 32;
134 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
135 writeb(0, &ch->ch_neo_uart->xonchar2);
137 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
138 writeb(0, &ch->ch_neo_uart->xoffchar2);
140 writeb(ier, &ch->ch_neo_uart->ier);
143 static void neo_set_ixoff_flow_control(struct jsm_channel *ch)
146 ier = readb(&ch->ch_neo_uart->ier);
147 efr = readb(&ch->ch_neo_uart->efr);
149 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXOFF FLOW\n");
160 writeb(0, &ch->ch_neo_uart->efr);
163 writeb(efr, &ch->ch_neo_uart->efr);
166 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
168 writeb(8, &ch->ch_neo_uart->tfifo);
169 ch->ch_t_tlevel = 8;
172 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
173 writeb(0, &ch->ch_neo_uart->xonchar2);
175 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
176 writeb(0, &ch->ch_neo_uart->xoffchar2);
178 writeb(ier, &ch->ch_neo_uart->ier);
181 static void neo_set_no_input_flow_control(struct jsm_channel *ch)
184 ier = readb(&ch->ch_neo_uart->ier);
185 efr = readb(&ch->ch_neo_uart->efr);
187 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Input FLOW\n");
195 if (ch->ch_c_iflag & IXON)
201 writeb(0, &ch->ch_neo_uart->efr);
204 writeb(efr, &ch->ch_neo_uart->efr);
207 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
209 ch->ch_r_watermark = 0;
211 writeb(16, &ch->ch_neo_uart->tfifo);
212 ch->ch_t_tlevel = 16;
214 writeb(16, &ch->ch_neo_uart->rfifo);
215 ch->ch_r_tlevel = 16;
217 writeb(ier, &ch->ch_neo_uart->ier);
220 static void neo_set_no_output_flow_control(struct jsm_channel *ch)
223 ier = readb(&ch->ch_neo_uart->ier);
224 efr = readb(&ch->ch_neo_uart->efr);
226 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Output FLOW\n");
233 if (ch->ch_c_iflag & IXOFF)
239 writeb(0, &ch->ch_neo_uart->efr);
242 writeb(efr, &ch->ch_neo_uart->efr);
245 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
247 ch->ch_r_watermark = 0;
249 writeb(16, &ch->ch_neo_uart->tfifo);
250 ch->ch_t_tlevel = 16;
252 writeb(16, &ch->ch_neo_uart->rfifo);
253 ch->ch_r_tlevel = 16;
255 writeb(ier, &ch->ch_neo_uart->ier);
258 static inline void neo_set_new_start_stop_chars(struct jsm_channel *ch)
262 if (ch->ch_c_cflag & CRTSCTS)
265 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "start\n");
268 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
269 writeb(0, &ch->ch_neo_uart->xonchar2);
271 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
272 writeb(0, &ch->ch_neo_uart->xoffchar2);
275 static void neo_copy_data_from_uart_to_queue(struct jsm_channel *ch)
286 head = ch->ch_r_head & RQUEUEMASK;
287 tail = ch->ch_r_tail & RQUEUEMASK;
290 linestatus = ch->ch_cached_lsr;
291 ch->ch_cached_lsr = 0;
304 if (!(ch->ch_flags & CH_FIFO_ENABLED))
307 total = readb(&ch->ch_neo_uart->rfifo);
333 linestatus = readb(&ch->ch_neo_uart->lsr);
360 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
365 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n);
371 memset(ch->ch_equeue + head, 0, n);
377 ch->ch_rxcount += n;
384 if (ch->ch_c_iflag & IGNBRK)
397 linestatus |= readb(&ch->ch_neo_uart->lsr);
405 ch->ch_cached_lsr = linestatus;
419 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
428 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
441 jsm_dbg(READ, &ch->ch_bd->pci_dev,
443 ch->ch_rqueue[tail], ch->ch_equeue[tail]);
445 ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK;
446 ch->ch_err_overrun++;
450 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1);
451 ch->ch_equeue[head] = (u8) linestatus;
453 jsm_dbg(READ, &ch->ch_bd->pci_dev, "DATA/LSR pair: %x %x\n",
454 ch->ch_rqueue[head], ch->ch_equeue[head]);
463 ch->ch_rxcount++;
469 ch->ch_r_head = head & RQUEUEMASK;
470 ch->ch_e_head = head & EQUEUEMASK;
471 jsm_input(ch);
474 static void neo_copy_data_from_queue_to_uart(struct jsm_channel *ch)
484 if (!ch)
487 circ = &ch->uart_port.state->xmit;
494 if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING))
499 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
500 u8 lsrbits = readb(&ch->ch_neo_uart->lsr);
502 ch->ch_cached_lsr |= lsrbits;
503 if (ch->ch_cached_lsr & UART_LSR_THRE) {
504 ch->ch_cached_lsr &= ~(UART_LSR_THRE);
506 writeb(circ->buf[circ->tail], &ch->ch_neo_uart->txrx);
507 jsm_dbg(WRITE, &ch->ch_bd->pci_dev,
510 ch->ch_txcount++;
518 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
521 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
539 memcpy_toio(&ch->ch_neo_uart->txrxburst, circ->buf + tail, s);
543 ch->ch_txcount += s;
550 if (len_written >= ch->ch_t_tlevel)
551 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
554 uart_write_wakeup(&ch->uart_port);
557 static void neo_parse_modem(struct jsm_channel *ch, u8 signals)
561 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
563 ch->ch_portnum, msignals);
570 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD);
572 uart_handle_cts_change(&ch->uart_port, msignals & UART_MSR_CTS);
574 ch->ch_mistat |= UART_MSR_DCD;
576 ch->ch_mistat &= ~UART_MSR_DCD;
579 ch->ch_mistat |= UART_MSR_DSR;
581 ch->ch_mistat &= ~UART_MSR_DSR;
584 ch->ch_mistat |= UART_MSR_RI;
586 ch->ch_mistat &= ~UART_MSR_RI;
589 ch->ch_mistat |= UART_MSR_CTS;
591 ch->ch_mistat &= ~UART_MSR_CTS;
593 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
595 ch->ch_portnum,
596 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
597 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
598 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
599 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
600 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
601 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD));
605 static void neo_assert_modem_signals(struct jsm_channel *ch)
607 if (!ch)
610 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
613 neo_pci_posting_flush(ch->ch_bd);
621 static void neo_flush_uart_write(struct jsm_channel *ch)
626 if (!ch)
629 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
634 tmp = readb(&ch->ch_neo_uart->isr_fcr);
636 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
644 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
653 static void neo_flush_uart_read(struct jsm_channel *ch)
658 if (!ch)
661 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr);
666 tmp = readb(&ch->ch_neo_uart->isr_fcr);
668 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
680 static void neo_clear_break(struct jsm_channel *ch)
684 spin_lock_irqsave(&ch->ch_lock, lock_flags);
687 if (ch->ch_flags & CH_BREAK_SENDING) {
688 u8 temp = readb(&ch->ch_neo_uart->lcr);
689 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
691 ch->ch_flags &= ~(CH_BREAK_SENDING);
692 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
697 neo_pci_posting_flush(ch->ch_bd);
699 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
707 struct jsm_channel *ch;
718 ch = brd->channels[port];
719 if (!ch)
725 isr = readb(&ch->ch_neo_uart->isr_fcr);
736 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d isr: %x\n",
741 neo_copy_data_from_uart_to_queue(ch);
744 spin_lock_irqsave(&ch->ch_lock, lock_flags);
745 jsm_check_queue_flow_control(ch);
746 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
751 spin_lock_irqsave(&ch->ch_lock, lock_flags);
752 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
753 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
754 neo_copy_data_from_queue_to_uart(ch);
758 cause = readb(&ch->ch_neo_uart->xoffchar1);
760 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
769 spin_lock_irqsave(&ch->ch_lock, lock_flags);
773 ch->ch_flags &= ~(CH_STOP);
775 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
781 ch->ch_flags |= CH_STOP;
782 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
785 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
789 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
797 cause = readb(&ch->ch_neo_uart->mcr);
800 spin_lock_irqsave(&ch->ch_lock, lock_flags);
803 ch->ch_mostat |= UART_MCR_RTS;
805 ch->ch_mostat &= ~(UART_MCR_RTS);
808 ch->ch_mostat |= UART_MCR_DTR;
810 ch->ch_mostat &= ~(UART_MCR_DTR);
812 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
816 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
818 spin_lock_irqsave(&ch->uart_port.lock, lock_flags);
819 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
820 spin_unlock_irqrestore(&ch->uart_port.lock, lock_flags);
826 struct jsm_channel *ch;
836 ch = brd->channels[port];
837 if (!ch)
840 linestatus = readb(&ch->ch_neo_uart->lsr);
842 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d port: %d linestatus: %x\n",
845 ch->ch_cached_lsr |= linestatus;
847 if (ch->ch_cached_lsr & UART_LSR_DR) {
849 neo_copy_data_from_uart_to_queue(ch);
850 spin_lock_irqsave(&ch->ch_lock, lock_flags);
851 jsm_check_queue_flow_control(ch);
852 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
862 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
872 ch->ch_err_parity++;
873 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. PAR ERR!\n",
878 ch->ch_err_frame++;
879 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. FRM ERR!\n",
884 ch->ch_err_break++;
885 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
897 ch->ch_err_overrun++;
898 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
904 spin_lock_irqsave(&ch->ch_lock, lock_flags);
905 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
906 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
909 neo_copy_data_from_queue_to_uart(ch);
912 spin_lock_irqsave(&ch->ch_lock, lock_flags);
913 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
914 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
917 neo_copy_data_from_queue_to_uart(ch);
925 static void neo_param(struct jsm_channel *ch)
933 bd = ch->ch_bd;
940 if ((ch->ch_c_cflag & (CBAUD)) == 0) {
941 ch->ch_r_head = ch->ch_r_tail = 0;
942 ch->ch_e_head = ch->ch_e_tail = 0;
944 neo_flush_uart_write(ch);
945 neo_flush_uart_read(ch);
947 ch->ch_flags |= (CH_BAUD0);
948 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
949 neo_assert_modem_signals(ch);
980 cflag = C_BAUD(ch->uart_port.state->port.tty);
989 if (ch->ch_flags & CH_BAUD0)
990 ch->ch_flags &= ~(CH_BAUD0);
993 if (ch->ch_c_cflag & PARENB)
996 if (!(ch->ch_c_cflag & PARODD))
1004 if (ch->ch_c_cflag & CMSPAR)
1008 if (ch->ch_c_cflag & CSTOPB)
1011 switch (ch->ch_c_cflag & CSIZE) {
1027 ier = readb(&ch->ch_neo_uart->ier);
1028 uart_lcr = readb(&ch->ch_neo_uart->lcr);
1030 quot = ch->ch_bd->bd_dividend / baud;
1033 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
1034 writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
1035 writeb((quot >> 8), &ch->ch_neo_uart->ier);
1036 writeb(lcr, &ch->ch_neo_uart->lcr);
1040 writeb(lcr, &ch->ch_neo_uart->lcr);
1042 if (ch->ch_c_cflag & CREAD)
1047 writeb(ier, &ch->ch_neo_uart->ier);
1050 neo_set_new_start_stop_chars(ch);
1052 if (ch->ch_c_cflag & CRTSCTS)
1053 neo_set_cts_flow_control(ch);
1054 else if (ch->ch_c_iflag & IXON) {
1056 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1057 neo_set_no_output_flow_control(ch);
1059 neo_set_ixon_flow_control(ch);
1062 neo_set_no_output_flow_control(ch);
1064 if (ch->ch_c_cflag & CRTSCTS)
1065 neo_set_rts_flow_control(ch);
1066 else if (ch->ch_c_iflag & IXOFF) {
1068 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1069 neo_set_no_input_flow_control(ch);
1071 neo_set_ixoff_flow_control(ch);
1074 neo_set_no_input_flow_control(ch);
1081 writeb(1, &ch->ch_neo_uart->rfifo);
1082 ch->ch_r_tlevel = 1;
1085 neo_assert_modem_signals(ch);
1088 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
1100 struct jsm_channel *ch;
1176 ch = brd->channels[port];
1177 if (!ch)
1180 neo_copy_data_from_uart_to_queue(ch);
1183 spin_lock_irqsave(&ch->ch_lock, lock_flags2);
1184 jsm_check_queue_flow_control(ch);
1185 spin_unlock_irqrestore(&ch->ch_lock, lock_flags2);
1244 static void neo_disable_receiver(struct jsm_channel *ch)
1246 u8 tmp = readb(&ch->ch_neo_uart->ier);
1248 writeb(tmp, &ch->ch_neo_uart->ier);
1251 neo_pci_posting_flush(ch->ch_bd);
1260 static void neo_enable_receiver(struct jsm_channel *ch)
1262 u8 tmp = readb(&ch->ch_neo_uart->ier);
1264 writeb(tmp, &ch->ch_neo_uart->ier);
1267 neo_pci_posting_flush(ch->ch_bd);
1270 static void neo_send_start_character(struct jsm_channel *ch)
1272 if (!ch)
1275 if (ch->ch_startc != __DISABLED_CHAR) {
1276 ch->ch_xon_sends++;
1277 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
1280 neo_pci_posting_flush(ch->ch_bd);
1284 static void neo_send_stop_character(struct jsm_channel *ch)
1286 if (!ch)
1289 if (ch->ch_stopc != __DISABLED_CHAR) {
1290 ch->ch_xoff_sends++;
1291 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
1294 neo_pci_posting_flush(ch->ch_bd);
1301 static void neo_uart_init(struct jsm_channel *ch)
1303 writeb(0, &ch->ch_neo_uart->ier);
1304 writeb(0, &ch->ch_neo_uart->efr);
1305 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
1308 readb(&ch->ch_neo_uart->txrx);
1309 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
1310 readb(&ch->ch_neo_uart->lsr);
1311 readb(&ch->ch_neo_uart->msr);
1313 ch->ch_flags |= CH_FIFO_ENABLED;
1316 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
1322 static void neo_uart_off(struct jsm_channel *ch)
1325 writeb(0, &ch->ch_neo_uart->efr);
1328 writeb(0, &ch->ch_neo_uart->ier);
1331 static u32 neo_get_uart_bytes_left(struct jsm_channel *ch)
1334 u8 lsr = readb(&ch->ch_neo_uart->lsr);
1337 ch->ch_cached_lsr |= lsr;
1343 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1351 static void neo_send_break(struct jsm_channel *ch)
1360 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1361 u8 temp = readb(&ch->ch_neo_uart->lcr);
1362 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1363 ch->ch_flags |= (CH_BREAK_SENDING);
1366 neo_pci_posting_flush(ch->ch_bd);
1378 static void neo_send_immediate_char(struct jsm_channel *ch, unsigned char c)
1380 if (!ch)
1383 writeb(c, &ch->ch_neo_uart->txrx);
1386 neo_pci_posting_flush(ch->ch_bd);