Lines Matching refs:ch
52 static void cls_set_cts_flow_control(struct jsm_channel *ch)
54 u8 lcrb = readb(&ch->ch_cls_uart->lcr);
55 u8 ier = readb(&ch->ch_cls_uart->ier);
62 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
64 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
70 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
73 writeb(lcrb, &ch->ch_cls_uart->lcr);
81 writeb(ier, &ch->ch_cls_uart->ier);
84 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
88 &ch->ch_cls_uart->isr_fcr);
90 ch->ch_t_tlevel = 16;
93 static void cls_set_ixon_flow_control(struct jsm_channel *ch)
95 u8 lcrb = readb(&ch->ch_cls_uart->lcr);
96 u8 ier = readb(&ch->ch_cls_uart->ier);
103 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
105 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
111 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
114 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
115 writeb(0, &ch->ch_cls_uart->lsr);
116 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
117 writeb(0, &ch->ch_cls_uart->spr);
120 writeb(lcrb, &ch->ch_cls_uart->lcr);
128 writeb(ier, &ch->ch_cls_uart->ier);
131 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
135 &ch->ch_cls_uart->isr_fcr);
138 static void cls_set_no_output_flow_control(struct jsm_channel *ch)
140 u8 lcrb = readb(&ch->ch_cls_uart->lcr);
141 u8 ier = readb(&ch->ch_cls_uart->ier);
148 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
150 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
156 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
159 writeb(lcrb, &ch->ch_cls_uart->lcr);
167 writeb(ier, &ch->ch_cls_uart->ier);
170 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
174 &ch->ch_cls_uart->isr_fcr);
176 ch->ch_r_watermark = 0;
177 ch->ch_t_tlevel = 16;
178 ch->ch_r_tlevel = 16;
181 static void cls_set_rts_flow_control(struct jsm_channel *ch)
183 u8 lcrb = readb(&ch->ch_cls_uart->lcr);
184 u8 ier = readb(&ch->ch_cls_uart->ier);
191 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
193 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
199 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
202 writeb(lcrb, &ch->ch_cls_uart->lcr);
206 writeb(ier, &ch->ch_cls_uart->ier);
209 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
213 &ch->ch_cls_uart->isr_fcr);
215 ch->ch_r_watermark = 4;
216 ch->ch_r_tlevel = 8;
219 static void cls_set_ixoff_flow_control(struct jsm_channel *ch)
221 u8 lcrb = readb(&ch->ch_cls_uart->lcr);
222 u8 ier = readb(&ch->ch_cls_uart->ier);
229 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
231 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
237 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
240 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
241 writeb(0, &ch->ch_cls_uart->lsr);
242 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
243 writeb(0, &ch->ch_cls_uart->spr);
246 writeb(lcrb, &ch->ch_cls_uart->lcr);
250 writeb(ier, &ch->ch_cls_uart->ier);
253 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
257 &ch->ch_cls_uart->isr_fcr);
260 static void cls_set_no_input_flow_control(struct jsm_channel *ch)
262 u8 lcrb = readb(&ch->ch_cls_uart->lcr);
263 u8 ier = readb(&ch->ch_cls_uart->ier);
270 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
272 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
278 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
281 writeb(lcrb, &ch->ch_cls_uart->lcr);
285 writeb(ier, &ch->ch_cls_uart->ier);
288 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
292 &ch->ch_cls_uart->isr_fcr);
294 ch->ch_t_tlevel = 16;
295 ch->ch_r_tlevel = 16;
305 static void cls_clear_break(struct jsm_channel *ch)
309 spin_lock_irqsave(&ch->ch_lock, lock_flags);
312 if (ch->ch_flags & CH_BREAK_SENDING) {
313 u8 temp = readb(&ch->ch_cls_uart->lcr);
315 writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr);
317 ch->ch_flags &= ~(CH_BREAK_SENDING);
318 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
322 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
325 static void cls_disable_receiver(struct jsm_channel *ch)
327 u8 tmp = readb(&ch->ch_cls_uart->ier);
330 writeb(tmp, &ch->ch_cls_uart->ier);
333 static void cls_enable_receiver(struct jsm_channel *ch)
335 u8 tmp = readb(&ch->ch_cls_uart->ier);
338 writeb(tmp, &ch->ch_cls_uart->ier);
342 static void cls_assert_modem_signals(struct jsm_channel *ch)
344 if (!ch)
347 writeb(ch->ch_mostat, &ch->ch_cls_uart->mcr);
350 static void cls_copy_data_from_uart_to_queue(struct jsm_channel *ch)
359 if (!ch)
362 spin_lock_irqsave(&ch->ch_lock, flags);
365 head = ch->ch_r_head & RQUEUEMASK;
366 tail = ch->ch_r_tail & RQUEUEMASK;
369 linestatus = ch->ch_cached_lsr;
370 ch->ch_cached_lsr = 0;
381 if (ch->ch_c_iflag & IGNBRK)
389 linestatus = readb(&ch->ch_cls_uart->lsr);
403 discard = readb(&ch->ch_cls_uart->txrx);
417 ch->ch_r_tail = tail;
418 ch->ch_err_overrun++;
422 ch->ch_equeue[head] = linestatus & (UART_LSR_BI | UART_LSR_PE
424 ch->ch_rqueue[head] = readb(&ch->ch_cls_uart->txrx);
428 if (ch->ch_equeue[head] & UART_LSR_PE)
429 ch->ch_err_parity++;
430 if (ch->ch_equeue[head] & UART_LSR_BI)
431 ch->ch_err_break++;
432 if (ch->ch_equeue[head] & UART_LSR_FE)
433 ch->ch_err_frame++;
437 ch->ch_rxcount++;
443 ch->ch_r_head = head & RQUEUEMASK;
444 ch->ch_e_head = head & EQUEUEMASK;
446 spin_unlock_irqrestore(&ch->ch_lock, flags);
449 static void cls_copy_data_from_queue_to_uart(struct jsm_channel *ch)
457 if (!ch)
460 circ = &ch->uart_port.state->xmit;
467 if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING))
471 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
484 writeb(circ->buf[tail], &ch->ch_cls_uart->txrx);
487 ch->ch_txcount++;
494 if (len_written > ch->ch_t_tlevel)
495 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
498 uart_write_wakeup(&ch->uart_port);
501 static void cls_parse_modem(struct jsm_channel *ch, u8 signals)
505 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
507 ch->ch_portnum, msignals);
517 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD);
519 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_CTS);
522 ch->ch_mistat |= UART_MSR_DCD;
524 ch->ch_mistat &= ~UART_MSR_DCD;
527 ch->ch_mistat |= UART_MSR_DSR;
529 ch->ch_mistat &= ~UART_MSR_DSR;
532 ch->ch_mistat |= UART_MSR_RI;
534 ch->ch_mistat &= ~UART_MSR_RI;
537 ch->ch_mistat |= UART_MSR_CTS;
539 ch->ch_mistat &= ~UART_MSR_CTS;
541 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
543 ch->ch_portnum,
544 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
545 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
546 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
547 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
548 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
549 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD));
555 struct jsm_channel *ch;
567 ch = brd->channels[port];
568 if (!ch)
573 isr = readb(&ch->ch_cls_uart->isr_fcr);
582 cls_copy_data_from_uart_to_queue(ch);
583 jsm_check_queue_flow_control(ch);
589 spin_lock_irqsave(&ch->ch_lock, flags);
590 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
591 spin_unlock_irqrestore(&ch->ch_lock, flags);
592 cls_copy_data_from_queue_to_uart(ch);
602 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
607 static void cls_flush_uart_write(struct jsm_channel *ch)
612 if (!ch)
616 &ch->ch_cls_uart->isr_fcr);
620 tmp = readb(&ch->ch_cls_uart->isr_fcr);
622 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
629 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
633 static void cls_flush_uart_read(struct jsm_channel *ch)
635 if (!ch)
652 static void cls_send_start_character(struct jsm_channel *ch)
654 if (!ch)
657 if (ch->ch_startc != __DISABLED_CHAR) {
658 ch->ch_xon_sends++;
659 writeb(ch->ch_startc, &ch->ch_cls_uart->txrx);
663 static void cls_send_stop_character(struct jsm_channel *ch)
665 if (!ch)
668 if (ch->ch_stopc != __DISABLED_CHAR) {
669 ch->ch_xoff_sends++;
670 writeb(ch->ch_stopc, &ch->ch_cls_uart->txrx);
678 static void cls_param(struct jsm_channel *ch)
689 bd = ch->ch_bd;
696 if ((ch->ch_c_cflag & (CBAUD)) == 0) {
697 ch->ch_r_head = 0;
698 ch->ch_r_tail = 0;
699 ch->ch_e_head = 0;
700 ch->ch_e_tail = 0;
702 cls_flush_uart_write(ch);
703 cls_flush_uart_read(ch);
706 ch->ch_flags |= (CH_BAUD0);
707 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
708 cls_assert_modem_signals(ch);
712 cflag = C_BAUD(ch->uart_port.state->port.tty);
721 if (ch->ch_flags & CH_BAUD0)
722 ch->ch_flags &= ~(CH_BAUD0);
724 if (ch->ch_c_cflag & PARENB)
727 if (!(ch->ch_c_cflag & PARODD))
735 if (ch->ch_c_cflag & CMSPAR)
739 if (ch->ch_c_cflag & CSTOPB)
742 switch (ch->ch_c_cflag & CSIZE) {
758 ier = readb(&ch->ch_cls_uart->ier);
759 uart_lcr = readb(&ch->ch_cls_uart->lcr);
761 quot = ch->ch_bd->bd_dividend / baud;
764 writeb(UART_LCR_DLAB, &ch->ch_cls_uart->lcr);
765 writeb((quot & 0xff), &ch->ch_cls_uart->txrx);
766 writeb((quot >> 8), &ch->ch_cls_uart->ier);
767 writeb(lcr, &ch->ch_cls_uart->lcr);
771 writeb(lcr, &ch->ch_cls_uart->lcr);
773 if (ch->ch_c_cflag & CREAD)
778 writeb(ier, &ch->ch_cls_uart->ier);
780 if (ch->ch_c_cflag & CRTSCTS)
781 cls_set_cts_flow_control(ch);
782 else if (ch->ch_c_iflag & IXON) {
787 if ((ch->ch_startc == __DISABLED_CHAR) ||
788 (ch->ch_stopc == __DISABLED_CHAR))
789 cls_set_no_output_flow_control(ch);
791 cls_set_ixon_flow_control(ch);
793 cls_set_no_output_flow_control(ch);
795 if (ch->ch_c_cflag & CRTSCTS)
796 cls_set_rts_flow_control(ch);
797 else if (ch->ch_c_iflag & IXOFF) {
802 if ((ch->ch_startc == __DISABLED_CHAR) ||
803 (ch->ch_stopc == __DISABLED_CHAR))
804 cls_set_no_input_flow_control(ch);
806 cls_set_ixoff_flow_control(ch);
808 cls_set_no_input_flow_control(ch);
810 cls_assert_modem_signals(ch);
813 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
859 static void cls_uart_init(struct jsm_channel *ch)
861 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
864 writeb(0, &ch->ch_cls_uart->ier);
870 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
872 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
877 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
880 writeb(lcrb, &ch->ch_cls_uart->lcr);
883 readb(&ch->ch_cls_uart->txrx);
886 &ch->ch_cls_uart->isr_fcr);
889 ch->ch_flags |= (CH_FIFO_ENABLED | CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
891 readb(&ch->ch_cls_uart->lsr);
892 readb(&ch->ch_cls_uart->msr);
898 static void cls_uart_off(struct jsm_channel *ch)
901 writeb(0, &ch->ch_cls_uart->ier);
910 static u32 cls_get_uart_bytes_left(struct jsm_channel *ch)
913 u8 lsr = readb(&ch->ch_cls_uart->lsr);
919 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
932 static void cls_send_break(struct jsm_channel *ch)
935 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
936 u8 temp = readb(&ch->ch_cls_uart->lcr);
938 writeb((temp | UART_LCR_SBC), &ch->ch_cls_uart->lcr);
939 ch->ch_flags |= (CH_BREAK_SENDING);
950 static void cls_send_immediate_char(struct jsm_channel *ch, unsigned char c)
952 writeb(c, &ch->ch_cls_uart->txrx);