Lines Matching refs:up
233 static void ip22zilog_maybe_update_regs(struct uart_ip22zilog_port *up,
236 if (!ZS_REGS_HELD(up)) {
237 if (ZS_TX_ACTIVE(up)) {
238 up->flags |= IP22ZILOG_FLAG_REGS_HELD;
240 __load_zsregs(channel, up->curregs);
248 static bool ip22zilog_receive_chars(struct uart_ip22zilog_port *up,
253 bool push = up->port.state != NULL;
271 ch &= up->parity_mask;
275 r1 |= up->tty_break;
279 up->port.icount.rx++;
281 up->tty_break = 0;
284 up->port.icount.brk++;
290 up->port.icount.parity++;
292 up->port.icount.frame++;
294 up->port.icount.overrun++;
295 r1 &= up->port.read_status_mask;
304 if (uart_handle_sysrq_char(&up->port, ch))
308 uart_insert_char(&up->port, r1, Rx_OVR, ch, flag);
313 static void ip22zilog_status_handle(struct uart_ip22zilog_port *up,
325 if (up->curregs[R15] & BRKIE) {
326 if ((status & BRK_ABRT) && !(up->prev_status & BRK_ABRT)) {
327 if (uart_handle_break(&up->port))
328 up->tty_break = Rx_SYS;
330 up->tty_break = Rx_BRK;
334 if (ZS_WANTS_MODEM_STATUS(up)) {
336 up->port.icount.dsr++;
342 if ((status ^ up->prev_status) ^ DCD)
343 uart_handle_dcd_change(&up->port,
345 if ((status ^ up->prev_status) ^ CTS)
346 uart_handle_cts_change(&up->port,
349 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
352 up->prev_status = status;
355 static void ip22zilog_transmit_chars(struct uart_ip22zilog_port *up,
360 if (ZS_IS_CONS(up)) {
376 up->flags &= ~IP22ZILOG_FLAG_TX_ACTIVE;
378 if (ZS_REGS_HELD(up)) {
379 __load_zsregs(channel, up->curregs);
380 up->flags &= ~IP22ZILOG_FLAG_REGS_HELD;
383 if (ZS_TX_STOPPED(up)) {
384 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED;
388 if (up->port.x_char) {
389 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
390 writeb(up->port.x_char, &channel->data);
394 up->port.icount.tx++;
395 up->port.x_char = 0;
399 if (up->port.state == NULL)
401 xmit = &up->port.state->xmit;
404 if (uart_tx_stopped(&up->port))
407 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
413 up->port.icount.tx++;
416 uart_write_wakeup(&up->port);
428 struct uart_ip22zilog_port *up = dev_id;
430 while (up) {
432 = ZILOG_CHANNEL_FROM_PORT(&up->port);
436 spin_lock(&up->port.lock);
446 push = ip22zilog_receive_chars(up, channel);
448 ip22zilog_status_handle(up, channel);
450 ip22zilog_transmit_chars(up, channel);
452 spin_unlock(&up->port.lock);
455 tty_flip_buffer_push(&up->port.state->port);
458 up = up->next;
459 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
462 spin_lock(&up->port.lock);
469 push = ip22zilog_receive_chars(up, channel);
471 ip22zilog_status_handle(up, channel);
473 ip22zilog_transmit_chars(up, channel);
475 spin_unlock(&up->port.lock);
478 tty_flip_buffer_push(&up->port.state->port);
480 up = up->next;
544 struct uart_ip22zilog_port *up =
561 up->curregs[R5] |= set_bits;
562 up->curregs[R5] &= ~clear_bits;
563 write_zsreg(channel, R5, up->curregs[R5]);
569 struct uart_ip22zilog_port *up =
572 up->flags |= IP22ZILOG_FLAG_TX_STOPPED;
578 struct uart_ip22zilog_port *up =
583 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
584 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED;
616 uart_write_wakeup(&up->port);
623 struct uart_ip22zilog_port *up = UART_ZILOG(port);
626 if (ZS_IS_CONS(up))
632 up->curregs[R1] &= ~RxINT_MASK;
633 ip22zilog_maybe_update_regs(up, channel);
639 struct uart_ip22zilog_port *up =
644 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
645 if (new_reg != up->curregs[R15]) {
646 up->curregs[R15] = new_reg;
649 write_zsreg(channel, R15, up->curregs[R15]);
656 struct uart_ip22zilog_port *up =
671 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
672 if (new_reg != up->curregs[R5]) {
673 up->curregs[R5] = new_reg;
676 write_zsreg(channel, R5, up->curregs[R5]);
682 static void __ip22zilog_reset(struct uart_ip22zilog_port *up)
687 if (up->flags & IP22ZILOG_FLAG_RESET_DONE)
691 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
699 if (!ZS_IS_CHANNEL_A(up)) {
700 up++;
701 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
707 up->flags |= IP22ZILOG_FLAG_RESET_DONE;
708 up->next->flags |= IP22ZILOG_FLAG_RESET_DONE;
711 static void __ip22zilog_startup(struct uart_ip22zilog_port *up)
715 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
717 __ip22zilog_reset(up);
719 __load_zsregs(channel, up->curregs);
721 write_zsreg(channel, R9, up->curregs[R9]);
722 up->prev_status = readb(&channel->control);
725 up->curregs[R3] |= RxENAB;
726 up->curregs[R5] |= TxENAB;
728 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
729 ip22zilog_maybe_update_regs(up, channel);
734 struct uart_ip22zilog_port *up = UART_ZILOG(port);
737 if (ZS_IS_CONS(up))
741 __ip22zilog_startup(up);
773 struct uart_ip22zilog_port *up = UART_ZILOG(port);
777 if (ZS_IS_CONS(up))
785 up->curregs[R3] &= ~RxENAB;
786 up->curregs[R5] &= ~TxENAB;
789 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
790 up->curregs[R5] &= ~SND_BRK;
791 ip22zilog_maybe_update_regs(up, channel);
800 ip22zilog_convert_to_zs(struct uart_ip22zilog_port *up, unsigned int cflag,
804 up->curregs[R10] = NRZ;
805 up->curregs[R11] = TCBR | RCBR;
808 up->curregs[R4] &= ~XCLK_MASK;
809 up->curregs[R4] |= X16CLK;
810 up->curregs[R12] = brg & 0xff;
811 up->curregs[R13] = (brg >> 8) & 0xff;
812 up->curregs[R14] = BRENAB;
815 up->curregs[3] &= ~RxN_MASK;
816 up->curregs[5] &= ~TxN_MASK;
819 up->curregs[3] |= Rx5;
820 up->curregs[5] |= Tx5;
821 up->parity_mask = 0x1f;
824 up->curregs[3] |= Rx6;
825 up->curregs[5] |= Tx6;
826 up->parity_mask = 0x3f;
829 up->curregs[3] |= Rx7;
830 up->curregs[5] |= Tx7;
831 up->parity_mask = 0x7f;
835 up->curregs[3] |= Rx8;
836 up->curregs[5] |= Tx8;
837 up->parity_mask = 0xff;
840 up->curregs[4] &= ~0x0c;
842 up->curregs[4] |= SB2;
844 up->curregs[4] |= SB1;
846 up->curregs[4] |= PAR_ENAB;
848 up->curregs[4] &= ~PAR_ENAB;
850 up->curregs[4] |= PAR_EVEN;
852 up->curregs[4] &= ~PAR_EVEN;
854 up->port.read_status_mask = Rx_OVR;
856 up->port.read_status_mask |= CRC_ERR | PAR_ERR;
858 up->port.read_status_mask |= BRK_ABRT;
860 up->port.ignore_status_mask = 0;
862 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
864 up->port.ignore_status_mask |= BRK_ABRT;
866 up->port.ignore_status_mask |= Rx_OVR;
870 up->port.ignore_status_mask = 0xff;
878 struct uart_ip22zilog_port *up =
885 spin_lock_irqsave(&up->port.lock, flags);
889 ip22zilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
891 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
892 up->flags |= IP22ZILOG_FLAG_MODEM_STATUS;
894 up->flags &= ~IP22ZILOG_FLAG_MODEM_STATUS;
896 ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
899 spin_unlock_irqrestore(&up->port.lock, flags);
1018 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index];
1021 spin_lock_irqsave(&up->port.lock, flags);
1022 uart_console_write(&up->port, s, count, ip22zilog_put_char);
1024 spin_unlock_irqrestore(&up->port.lock, flags);
1029 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index];
1035 up->flags |= IP22ZILOG_FLAG_IS_CONS;
1039 spin_lock_irqsave(&up->port.lock, flags);
1041 up->curregs[R15] |= BRKIE;
1043 __ip22zilog_startup(up);
1045 spin_unlock_irqrestore(&up->port.lock, flags);
1049 return uart_set_options(&up->port, con, baud, parity, bits, flow);
1080 struct uart_ip22zilog_port *up;
1091 up = &ip22zilog_port_table[0];
1093 up[channel].next = &up[channel - 1];
1094 up[channel].next = NULL;
1100 up[(chip * 2) + 0].port.membase = (char *) &rp->channelB;
1101 up[(chip * 2) + 1].port.membase = (char *) &rp->channelA;
1104 up[(chip * 2) + 0].port.mapbase =
1106 up[(chip * 2) + 1].port.mapbase =
1111 up[(chip * 2) + 0].port.iotype = UPIO_MEM;
1112 up[(chip * 2) + 0].port.irq = zilog_irq;
1113 up[(chip * 2) + 0].port.uartclk = ZS_CLOCK;
1114 up[(chip * 2) + 0].port.fifosize = 1;
1115 up[(chip * 2) + 0].port.has_sysrq = sysrq_on;
1116 up[(chip * 2) + 0].port.ops = &ip22zilog_pops;
1117 up[(chip * 2) + 0].port.type = PORT_IP22ZILOG;
1118 up[(chip * 2) + 0].port.flags = 0;
1119 up[(chip * 2) + 0].port.line = (chip * 2) + 0;
1120 up[(chip * 2) + 0].flags = 0;
1123 up[(chip * 2) + 1].port.iotype = UPIO_MEM;
1124 up[(chip * 2) + 1].port.irq = zilog_irq;
1125 up[(chip * 2) + 1].port.uartclk = ZS_CLOCK;
1126 up[(chip * 2) + 1].port.fifosize = 1;
1127 up[(chip * 2) + 1].port.has_sysrq = sysrq_on;
1128 up[(chip * 2) + 1].port.ops = &ip22zilog_pops;
1129 up[(chip * 2) + 1].port.type = PORT_IP22ZILOG;
1130 up[(chip * 2) + 1].port.line = (chip * 2) + 1;
1131 up[(chip * 2) + 1].flags |= IP22ZILOG_FLAG_IS_CHANNEL_A;
1135 struct uart_ip22zilog_port *up = &ip22zilog_port_table[channel];
1139 up->parity_mask = 0xff;
1140 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1141 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1142 up->curregs[R3] = RxENAB | Rx8;
1143 up->curregs[R5] = TxENAB | Tx8;
1144 up->curregs[R9] = NV | MIE;
1145 up->curregs[R10] = NRZ;
1146 up->curregs[R11] = TCBR | RCBR;
1148 up->curregs[R12] = (brg & 0xff);
1149 up->curregs[R13] = (brg >> 8) & 0xff;
1150 up->curregs[R14] = BRENAB;
1172 struct uart_ip22zilog_port *up = &ip22zilog_port_table[i];
1174 uart_add_one_port(&ip22zilog_reg, &up->port);
1193 struct uart_ip22zilog_port *up;
1196 up = &ip22zilog_port_table[i];
1198 uart_remove_one_port(&ip22zilog_reg, &up->port);
1202 up = &ip22zilog_port_table[0];
1204 if (up[(i * 2) + 0].port.mapbase) {
1205 iounmap((void*)up[(i * 2) + 0].port.mapbase);
1206 up[(i * 2) + 0].port.mapbase = 0;
1208 if (up[(i * 2) + 1].port.mapbase) {
1209 iounmap((void*)up[(i * 2) + 1].port.mapbase);
1210 up[(i * 2) + 1].port.mapbase = 0;