Lines Matching defs:channel
51 #define ZS_WSYNC(channel) do { } while (0)
109 static unsigned char read_zsreg(struct zilog_channel *channel,
114 writeb(reg, &channel->control);
116 retval = readb(&channel->control);
122 static void write_zsreg(struct zilog_channel *channel,
125 writeb(reg, &channel->control);
127 writeb(value, &channel->control);
131 static void ip22zilog_clear_fifo(struct zilog_channel *channel)
138 regval = readb(&channel->control);
143 regval = read_zsreg(channel, R1);
144 readb(&channel->data);
148 writeb(ERR_RES, &channel->control);
150 ZS_WSYNC(channel);
158 static void __load_zsregs(struct zilog_channel *channel, unsigned char *regs)
164 unsigned char stat = read_zsreg(channel, R1);
170 writeb(ERR_RES, &channel->control);
172 ZS_WSYNC(channel);
174 ip22zilog_clear_fifo(channel);
177 write_zsreg(channel, R1,
181 write_zsreg(channel, R4, regs[R4]);
184 write_zsreg(channel, R10, regs[R10]);
187 write_zsreg(channel, R3, regs[R3] & ~RxENAB);
188 write_zsreg(channel, R5, regs[R5] & ~TxENAB);
191 write_zsreg(channel, R6, regs[R6]);
192 write_zsreg(channel, R7, regs[R7]);
200 write_zsreg(channel, R14, regs[R14] & ~BRENAB);
203 write_zsreg(channel, R11, regs[R11]);
206 write_zsreg(channel, R12, regs[R12]);
207 write_zsreg(channel, R13, regs[R13]);
210 write_zsreg(channel, R14, regs[R14]);
213 write_zsreg(channel, R15, regs[R15]);
216 write_zsreg(channel, R0, RES_EXT_INT);
217 write_zsreg(channel, R0, RES_EXT_INT);
220 write_zsreg(channel, R3, regs[R3]);
221 write_zsreg(channel, R5, regs[R5]);
224 write_zsreg(channel, R1, regs[R1]);
227 /* Reprogram the Zilog channel HW registers with the copies found in the
234 struct zilog_channel *channel)
240 __load_zsregs(channel, up->curregs);
249 struct zilog_channel *channel)
256 ch = readb(&channel->control);
261 r1 = read_zsreg(channel, R1);
263 writeb(ERR_RES, &channel->control);
265 ZS_WSYNC(channel);
268 ch = readb(&channel->data);
314 struct zilog_channel *channel)
318 status = readb(&channel->control);
321 writeb(RES_EXT_INT, &channel->control);
323 ZS_WSYNC(channel);
356 struct zilog_channel *channel)
361 unsigned char status = readb(&channel->control);
379 __load_zsregs(channel, up->curregs);
390 writeb(up->port.x_char, &channel->data);
392 ZS_WSYNC(channel);
408 writeb(xmit->buf[xmit->tail], &channel->data);
410 ZS_WSYNC(channel);
421 writeb(RES_Tx_P, &channel->control);
423 ZS_WSYNC(channel);
431 struct zilog_channel *channel
437 r3 = read_zsreg(channel, R3);
441 writeb(RES_H_IUS, &channel->control);
443 ZS_WSYNC(channel);
446 push = ip22zilog_receive_chars(up, channel);
448 ip22zilog_status_handle(up, channel);
450 ip22zilog_transmit_chars(up, channel);
459 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
464 writeb(RES_H_IUS, &channel->control);
466 ZS_WSYNC(channel);
469 push = ip22zilog_receive_chars(up, channel);
471 ip22zilog_status_handle(up, channel);
473 ip22zilog_transmit_chars(up, channel);
491 struct zilog_channel *channel;
494 channel = ZILOG_CHANNEL_FROM_PORT(port);
495 status = readb(&channel->control);
546 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
563 write_zsreg(channel, R5, up->curregs[R5]);
580 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
586 status = readb(&channel->control);
597 writeb(port->x_char, &channel->data);
599 ZS_WSYNC(channel);
608 writeb(xmit->buf[xmit->tail], &channel->data);
610 ZS_WSYNC(channel);
624 struct zilog_channel *channel;
629 channel = ZILOG_CHANNEL_FROM_PORT(port);
633 ip22zilog_maybe_update_regs(up, channel);
641 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
649 write_zsreg(channel, R15, up->curregs[R15]);
658 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
676 write_zsreg(channel, R5, up->curregs[R5]);
684 struct zilog_channel *channel;
691 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
693 unsigned char stat = read_zsreg(channel, R1);
701 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
703 write_zsreg(channel, R9, FHWRES);
705 (void) read_zsreg(channel, R0);
713 struct zilog_channel *channel;
715 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
719 __load_zsregs(channel, up->curregs);
721 write_zsreg(channel, R9, up->curregs[R9]);
722 up->prev_status = readb(&channel->control);
729 ip22zilog_maybe_update_regs(up, channel);
774 struct zilog_channel *channel;
782 channel = ZILOG_CHANNEL_FROM_PORT(port);
791 ip22zilog_maybe_update_regs(up, channel);
995 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
1002 unsigned char val = readb(&channel->control);
1010 writeb(ch, &channel->data);
1012 ZS_WSYNC(channel);
1082 int channel, chip;
1087 for (channel = 0; channel < NUM_CHANNELS; channel++)
1088 spin_lock_init(&ip22zilog_port_table[channel].port.lock);
1092 for (channel = NUM_CHANNELS - 1 ; channel > 0; channel--)
1093 up[channel].next = &up[channel - 1];
1094 up[channel].next = NULL;
1134 for (channel = 0; channel < NUM_CHANNELS; channel++) {
1135 struct uart_ip22zilog_port *up = &ip22zilog_port_table[channel];