Lines Matching refs:sport
294 static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
298 sport->ucr1 = val;
301 sport->ucr2 = val;
304 sport->ucr3 = val;
307 sport->ucr4 = val;
310 sport->ufcr = val;
315 writel(val, sport->port.membase + offset);
318 static u32 imx_uart_readl(struct imx_port *sport, u32 offset)
322 return sport->ucr1;
331 if (!(sport->ucr2 & UCR2_SRST))
332 sport->ucr2 = readl(sport->port.membase + offset);
333 return sport->ucr2;
336 return sport->ucr3;
339 return sport->ucr4;
342 return sport->ufcr;
345 return readl(sport->port.membase + offset);
349 static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
351 return sport->devdata->uts_reg;
354 static inline int imx_uart_is_imx1(struct imx_port *sport)
356 return sport->devdata->devtype == IMX1_UART;
359 static inline int imx_uart_is_imx21(struct imx_port *sport)
361 return sport->devdata->devtype == IMX21_UART;
364 static inline int imx_uart_is_imx53(struct imx_port *sport)
366 return sport->devdata->devtype == IMX53_UART;
369 static inline int imx_uart_is_imx6q(struct imx_port *sport)
371 return sport->devdata->devtype == IMX6Q_UART;
377 static void imx_uart_ucrs_save(struct imx_port *sport,
381 ucr->ucr1 = imx_uart_readl(sport, UCR1);
382 ucr->ucr2 = imx_uart_readl(sport, UCR2);
383 ucr->ucr3 = imx_uart_readl(sport, UCR3);
386 static void imx_uart_ucrs_restore(struct imx_port *sport,
390 imx_uart_writel(sport, ucr->ucr1, UCR1);
391 imx_uart_writel(sport, ucr->ucr2, UCR2);
392 imx_uart_writel(sport, ucr->ucr3, UCR3);
397 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
401 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
405 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
410 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
425 struct imx_port *sport = (struct imx_port *)port;
428 ucr1 = imx_uart_readl(sport, UCR1);
429 ucr2 = imx_uart_readl(sport, UCR2);
433 if (sport->dma_is_enabled) {
441 imx_uart_writel(sport, ucr2, UCR2);
442 imx_uart_writel(sport, ucr1, UCR1);
448 struct imx_port *sport = (struct imx_port *)port;
451 if (sport->tx_state == OFF)
458 if (sport->dma_is_txing)
461 ucr1 = imx_uart_readl(sport, UCR1);
462 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
464 ucr4 = imx_uart_readl(sport, UCR4);
465 usr2 = imx_uart_readl(sport, USR2);
472 imx_uart_writel(sport, ucr4, UCR4);
476 if (sport->tx_state == SEND) {
477 sport->tx_state = WAIT_AFTER_SEND;
478 start_hrtimer_ms(&sport->trigger_stop_tx,
483 if (sport->tx_state == WAIT_AFTER_RTS ||
484 sport->tx_state == WAIT_AFTER_SEND) {
487 hrtimer_try_to_cancel(&sport->trigger_start_tx);
489 ucr2 = imx_uart_readl(sport, UCR2);
491 imx_uart_rts_active(sport, &ucr2);
493 imx_uart_rts_inactive(sport, &ucr2);
494 imx_uart_writel(sport, ucr2, UCR2);
498 sport->tx_state = OFF;
501 sport->tx_state = OFF;
508 struct imx_port *sport = (struct imx_port *)port;
511 ucr1 = imx_uart_readl(sport, UCR1);
512 ucr2 = imx_uart_readl(sport, UCR2);
513 ucr4 = imx_uart_readl(sport, UCR4);
515 if (sport->dma_is_enabled) {
522 imx_uart_writel(sport, ucr1, UCR1);
523 imx_uart_writel(sport, ucr4, UCR4);
526 imx_uart_writel(sport, ucr2, UCR2);
532 struct imx_port *sport = (struct imx_port *)port;
534 mod_timer(&sport->timer, jiffies);
536 mctrl_gpio_enable_ms(sport->gpios);
539 static void imx_uart_dma_tx(struct imx_port *sport);
542 static inline void imx_uart_transmit_buffer(struct imx_port *sport)
544 struct circ_buf *xmit = &sport->port.state->xmit;
546 if (sport->port.x_char) {
548 imx_uart_writel(sport, sport->port.x_char, URTX0);
549 sport->port.icount.tx++;
550 sport->port.x_char = 0;
554 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
555 imx_uart_stop_tx(&sport->port);
559 if (sport->dma_is_enabled) {
565 ucr1 = imx_uart_readl(sport, UCR1);
567 if (sport->dma_is_txing) {
569 imx_uart_writel(sport, ucr1, UCR1);
571 imx_uart_writel(sport, ucr1, UCR1);
572 imx_uart_dma_tx(sport);
579 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) {
582 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0);
584 sport->port.icount.tx++;
588 uart_write_wakeup(&sport->port);
591 imx_uart_stop_tx(&sport->port);
596 struct imx_port *sport = data;
597 struct scatterlist *sgl = &sport->tx_sgl[0];
598 struct circ_buf *xmit = &sport->port.state->xmit;
602 spin_lock_irqsave(&sport->port.lock, flags);
604 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
606 ucr1 = imx_uart_readl(sport, UCR1);
608 imx_uart_writel(sport, ucr1, UCR1);
611 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
612 sport->port.icount.tx += sport->tx_bytes;
614 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
616 sport->dma_is_txing = 0;
619 uart_write_wakeup(&sport->port);
621 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
622 imx_uart_dma_tx(sport);
623 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
624 u32 ucr4 = imx_uart_readl(sport, UCR4);
626 imx_uart_writel(sport, ucr4, UCR4);
629 spin_unlock_irqrestore(&sport->port.lock, flags);
633 static void imx_uart_dma_tx(struct imx_port *sport)
635 struct circ_buf *xmit = &sport->port.state->xmit;
636 struct scatterlist *sgl = sport->tx_sgl;
638 struct dma_chan *chan = sport->dma_chan_tx;
639 struct device *dev = sport->port.dev;
643 if (sport->dma_is_txing)
646 ucr4 = imx_uart_readl(sport, UCR4);
648 imx_uart_writel(sport, ucr4, UCR4);
650 sport->tx_bytes = uart_circ_chars_pending(xmit);
653 sport->dma_tx_nents = 1;
654 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
656 sport->dma_tx_nents = 2;
663 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
671 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
677 desc->callback_param = sport;
682 ucr1 = imx_uart_readl(sport, UCR1);
684 imx_uart_writel(sport, ucr1, UCR1);
687 sport->dma_is_txing = 1;
696 struct imx_port *sport = (struct imx_port *)port;
699 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit))
703 * We cannot simply do nothing here if sport->tx_state == SEND already
709 if (sport->tx_state == OFF) {
710 u32 ucr2 = imx_uart_readl(sport, UCR2);
712 imx_uart_rts_active(sport, &ucr2);
714 imx_uart_rts_inactive(sport, &ucr2);
715 imx_uart_writel(sport, ucr2, UCR2);
720 sport->tx_state = WAIT_AFTER_RTS;
721 start_hrtimer_ms(&sport->trigger_start_tx,
726 if (sport->tx_state == WAIT_AFTER_SEND
727 || sport->tx_state == WAIT_AFTER_RTS) {
729 hrtimer_try_to_cancel(&sport->trigger_stop_tx);
736 if (!sport->dma_is_enabled) {
737 u32 ucr4 = imx_uart_readl(sport, UCR4);
739 imx_uart_writel(sport, ucr4, UCR4);
742 sport->tx_state = SEND;
745 sport->tx_state = SEND;
748 if (!sport->dma_is_enabled) {
749 ucr1 = imx_uart_readl(sport, UCR1);
750 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
753 if (sport->dma_is_enabled) {
754 if (sport->port.x_char) {
757 ucr1 = imx_uart_readl(sport, UCR1);
760 imx_uart_writel(sport, ucr1, UCR1);
766 imx_uart_dma_tx(sport);
773 struct imx_port *sport = dev_id;
776 imx_uart_writel(sport, USR1_RTSD, USR1);
777 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
778 uart_handle_cts_change(&sport->port, !!usr1);
779 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
786 struct imx_port *sport = dev_id;
789 spin_lock(&sport->port.lock);
793 spin_unlock(&sport->port.lock);
800 struct imx_port *sport = dev_id;
802 spin_lock(&sport->port.lock);
803 imx_uart_transmit_buffer(sport);
804 spin_unlock(&sport->port.lock);
810 struct imx_port *sport = dev_id;
812 struct tty_port *port = &sport->port.state->port;
814 while (imx_uart_readl(sport, USR2) & USR2_RDR) {
818 sport->port.icount.rx++;
820 rx = imx_uart_readl(sport, URXD0);
822 usr2 = imx_uart_readl(sport, USR2);
824 imx_uart_writel(sport, USR2_BRCD, USR2);
825 if (uart_handle_break(&sport->port))
829 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
834 sport->port.icount.brk++;
836 sport->port.icount.parity++;
838 sport->port.icount.frame++;
840 sport->port.icount.overrun++;
842 if (rx & sport->port.ignore_status_mask) {
848 rx &= (sport->port.read_status_mask | 0xFF);
859 sport->port.sysrq = 0;
862 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
866 sport->port.icount.buf_overrun++;
877 struct imx_port *sport = dev_id;
880 spin_lock(&sport->port.lock);
884 spin_unlock(&sport->port.lock);
889 static void imx_uart_clear_rx_errors(struct imx_port *sport);
894 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
897 unsigned usr1 = imx_uart_readl(sport, USR1);
898 unsigned usr2 = imx_uart_readl(sport, USR2);
907 if (sport->dte_mode)
908 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
917 static void imx_uart_mctrl_check(struct imx_port *sport)
921 status = imx_uart_get_hwmctrl(sport);
922 changed = status ^ sport->old_status;
927 sport->old_status = status;
930 sport->port.icount.rng++;
932 sport->port.icount.dsr++;
934 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
936 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
938 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
943 struct imx_port *sport = dev_id;
953 spin_lock_irqsave(&sport->port.lock, flags);
955 usr1 = imx_uart_readl(sport, USR1);
956 usr2 = imx_uart_readl(sport, USR2);
957 ucr1 = imx_uart_readl(sport, UCR1);
958 ucr2 = imx_uart_readl(sport, UCR2);
959 ucr3 = imx_uart_readl(sport, UCR3);
960 ucr4 = imx_uart_readl(sport, UCR4);
988 imx_uart_writel(sport, USR1_AGTIM, USR1);
995 imx_uart_transmit_buffer(sport);
1000 imx_uart_writel(sport, USR1_DTRD, USR1);
1002 imx_uart_mctrl_check(sport);
1013 imx_uart_writel(sport, USR1_AWAKE, USR1);
1018 sport->port.icount.overrun++;
1019 imx_uart_writel(sport, USR2_ORE, USR2);
1023 spin_unlock_irqrestore(&sport->port.lock, flags);
1033 struct imx_port *sport = (struct imx_port *)port;
1036 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1039 if (sport->dma_is_txing)
1048 struct imx_port *sport = (struct imx_port *)port;
1049 unsigned int ret = imx_uart_get_hwmctrl(sport);
1051 mctrl_gpio_get(sport->gpios, &ret);
1059 struct imx_port *sport = (struct imx_port *)port;
1069 ucr2 = imx_uart_readl(sport, UCR2);
1081 imx_uart_writel(sport, ucr2, UCR2);
1084 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
1087 imx_uart_writel(sport, ucr3, UCR3);
1089 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
1092 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1094 mctrl_gpio_set(sport->gpios, mctrl);
1102 struct imx_port *sport = (struct imx_port *)port;
1106 spin_lock_irqsave(&sport->port.lock, flags);
1108 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1113 imx_uart_writel(sport, ucr1, UCR1);
1115 spin_unlock_irqrestore(&sport->port.lock, flags);
1124 struct imx_port *sport = from_timer(sport, t, timer);
1127 if (sport->port.state) {
1128 spin_lock_irqsave(&sport->port.lock, flags);
1129 imx_uart_mctrl_check(sport);
1130 spin_unlock_irqrestore(&sport->port.lock, flags);
1132 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1146 struct imx_port *sport = data;
1147 struct dma_chan *chan = sport->dma_chan_rx;
1148 struct scatterlist *sgl = &sport->rx_sgl;
1149 struct tty_port *port = &sport->port.state->port;
1151 struct circ_buf *rx_ring = &sport->rx_ring;
1157 status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1160 imx_uart_clear_rx_errors(sport);
1164 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1181 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1191 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1195 sport->rx_buf + rx_ring->tail, r_bytes);
1198 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1202 sport->port.icount.buf_overrun++;
1204 sport->port.icount.rx += w_bytes;
1213 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1221 static int imx_uart_start_rx_dma(struct imx_port *sport)
1223 struct scatterlist *sgl = &sport->rx_sgl;
1224 struct dma_chan *chan = sport->dma_chan_rx;
1225 struct device *dev = sport->port.dev;
1229 sport->rx_ring.head = 0;
1230 sport->rx_ring.tail = 0;
1231 sport->rx_periods = RX_DMA_PERIODS;
1233 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
1241 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1250 desc->callback_param = sport;
1253 sport->dma_is_rxing = 1;
1254 sport->rx_cookie = dmaengine_submit(desc);
1259 static void imx_uart_clear_rx_errors(struct imx_port *sport)
1261 struct tty_port *port = &sport->port.state->port;
1264 usr1 = imx_uart_readl(sport, USR1);
1265 usr2 = imx_uart_readl(sport, USR2);
1268 sport->port.icount.brk++;
1269 imx_uart_writel(sport, USR2_BRCD, USR2);
1270 uart_handle_break(&sport->port);
1272 sport->port.icount.buf_overrun++;
1276 sport->port.icount.frame++;
1277 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1279 sport->port.icount.parity++;
1280 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1285 sport->port.icount.overrun++;
1286 imx_uart_writel(sport, USR2_ORE, USR2);
1296 static void imx_uart_setup_ufcr(struct imx_port *sport,
1302 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1304 imx_uart_writel(sport, val, UFCR);
1307 static void imx_uart_dma_exit(struct imx_port *sport)
1309 if (sport->dma_chan_rx) {
1310 dmaengine_terminate_sync(sport->dma_chan_rx);
1311 dma_release_channel(sport->dma_chan_rx);
1312 sport->dma_chan_rx = NULL;
1313 sport->rx_cookie = -EINVAL;
1314 kfree(sport->rx_buf);
1315 sport->rx_buf = NULL;
1318 if (sport->dma_chan_tx) {
1319 dmaengine_terminate_sync(sport->dma_chan_tx);
1320 dma_release_channel(sport->dma_chan_tx);
1321 sport->dma_chan_tx = NULL;
1325 static int imx_uart_dma_init(struct imx_port *sport)
1328 struct device *dev = sport->port.dev;
1332 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1333 if (!sport->dma_chan_rx) {
1340 slave_config.src_addr = sport->port.mapbase + URXD0;
1344 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1350 sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL);
1351 if (!sport->rx_buf) {
1355 sport->rx_ring.buf = sport->rx_buf;
1358 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1359 if (!sport->dma_chan_tx) {
1366 slave_config.dst_addr = sport->port.mapbase + URTX0;
1369 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1377 imx_uart_dma_exit(sport);
1381 static void imx_uart_enable_dma(struct imx_port *sport)
1385 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1388 ucr1 = imx_uart_readl(sport, UCR1);
1390 imx_uart_writel(sport, ucr1, UCR1);
1392 sport->dma_is_enabled = 1;
1395 static void imx_uart_disable_dma(struct imx_port *sport)
1400 ucr1 = imx_uart_readl(sport, UCR1);
1402 imx_uart_writel(sport, ucr1, UCR1);
1404 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1406 sport->dma_is_enabled = 0;
1414 struct imx_port *sport = (struct imx_port *)port;
1420 retval = clk_prepare_enable(sport->clk_per);
1423 retval = clk_prepare_enable(sport->clk_ipg);
1425 clk_disable_unprepare(sport->clk_per);
1429 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1434 ucr4 = imx_uart_readl(sport, UCR4);
1440 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1443 if (!uart_console(port) && imx_uart_dma_init(sport) == 0)
1446 spin_lock_irqsave(&sport->port.lock, flags);
1450 ucr2 = imx_uart_readl(sport, UCR2);
1452 imx_uart_writel(sport, ucr2, UCR2);
1454 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1460 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1461 imx_uart_writel(sport, USR2_ORE, USR2);
1463 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1465 if (sport->have_rtscts)
1468 imx_uart_writel(sport, ucr1, UCR1);
1470 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
1473 if (sport->inverted_rx)
1475 imx_uart_writel(sport, ucr4, UCR4);
1477 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
1481 if (sport->inverted_tx)
1484 if (!imx_uart_is_imx1(sport)) {
1487 if (sport->dte_mode)
1491 imx_uart_writel(sport, ucr3, UCR3);
1493 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1495 if (!sport->have_rtscts)
1501 if (!imx_uart_is_imx1(sport))
1503 imx_uart_writel(sport, ucr2, UCR2);
1508 imx_uart_enable_ms(&sport->port);
1511 imx_uart_enable_dma(sport);
1512 imx_uart_start_rx_dma(sport);
1514 ucr1 = imx_uart_readl(sport, UCR1);
1516 imx_uart_writel(sport, ucr1, UCR1);
1518 ucr2 = imx_uart_readl(sport, UCR2);
1520 imx_uart_writel(sport, ucr2, UCR2);
1523 spin_unlock_irqrestore(&sport->port.lock, flags);
1530 struct imx_port *sport = (struct imx_port *)port;
1534 if (sport->dma_is_enabled) {
1535 dmaengine_terminate_sync(sport->dma_chan_tx);
1536 if (sport->dma_is_txing) {
1537 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1538 sport->dma_tx_nents, DMA_TO_DEVICE);
1539 sport->dma_is_txing = 0;
1541 dmaengine_terminate_sync(sport->dma_chan_rx);
1542 if (sport->dma_is_rxing) {
1543 dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1545 sport->dma_is_rxing = 0;
1548 spin_lock_irqsave(&sport->port.lock, flags);
1551 imx_uart_disable_dma(sport);
1552 spin_unlock_irqrestore(&sport->port.lock, flags);
1553 imx_uart_dma_exit(sport);
1556 mctrl_gpio_disable_ms(sport->gpios);
1558 spin_lock_irqsave(&sport->port.lock, flags);
1559 ucr2 = imx_uart_readl(sport, UCR2);
1561 imx_uart_writel(sport, ucr2, UCR2);
1562 spin_unlock_irqrestore(&sport->port.lock, flags);
1567 del_timer_sync(&sport->timer);
1573 spin_lock_irqsave(&sport->port.lock, flags);
1575 ucr1 = imx_uart_readl(sport, UCR1);
1577 imx_uart_writel(sport, ucr1, UCR1);
1579 ucr4 = imx_uart_readl(sport, UCR4);
1581 imx_uart_writel(sport, ucr4, UCR4);
1583 spin_unlock_irqrestore(&sport->port.lock, flags);
1585 clk_disable_unprepare(sport->clk_per);
1586 clk_disable_unprepare(sport->clk_ipg);
1592 struct imx_port *sport = (struct imx_port *)port;
1593 struct scatterlist *sgl = &sport->tx_sgl[0];
1597 if (!sport->dma_chan_tx)
1600 sport->tx_bytes = 0;
1601 dmaengine_terminate_all(sport->dma_chan_tx);
1602 if (sport->dma_is_txing) {
1605 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1607 ucr1 = imx_uart_readl(sport, UCR1);
1609 imx_uart_writel(sport, ucr1, UCR1);
1610 sport->dma_is_txing = 0;
1624 ubir = imx_uart_readl(sport, UBIR);
1625 ubmr = imx_uart_readl(sport, UBMR);
1626 uts = imx_uart_readl(sport, IMX21_UTS);
1628 ucr2 = imx_uart_readl(sport, UCR2);
1630 imx_uart_writel(sport, ucr2, UCR2);
1632 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1636 imx_uart_writel(sport, ubir, UBIR);
1637 imx_uart_writel(sport, ubmr, UBMR);
1638 imx_uart_writel(sport, uts, IMX21_UTS);
1645 struct imx_port *sport = (struct imx_port *)port;
1664 del_timer_sync(&sport->timer);
1672 spin_lock_irqsave(&sport->port.lock, flags);
1678 old_ucr2 = imx_uart_readl(sport, UCR2);
1685 if (!sport->have_rtscts)
1695 imx_uart_rts_active(sport, &ucr2);
1697 imx_uart_rts_inactive(sport, &ucr2);
1718 sport->port.read_status_mask = 0;
1720 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1722 sport->port.read_status_mask |= URXD_BRK;
1727 sport->port.ignore_status_mask = 0;
1729 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1731 sport->port.ignore_status_mask |= URXD_BRK;
1737 sport->port.ignore_status_mask |= URXD_OVRRUN;
1741 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1749 div = sport->port.uartclk / (baud * 16);
1751 baud = sport->port.uartclk / (quot * 16);
1753 div = sport->port.uartclk / (baud * 16);
1759 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1762 tdiv64 = sport->port.uartclk;
1771 ufcr = imx_uart_readl(sport, UFCR);
1773 imx_uart_writel(sport, ufcr, UFCR);
1784 old_ubir = imx_uart_readl(sport, UBIR);
1785 old_ubmr = imx_uart_readl(sport, UBMR);
1787 imx_uart_writel(sport, num, UBIR);
1788 imx_uart_writel(sport, denom, UBMR);
1791 if (!imx_uart_is_imx1(sport))
1792 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1795 imx_uart_writel(sport, ucr2, UCR2);
1797 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1798 imx_uart_enable_ms(&sport->port);
1800 spin_unlock_irqrestore(&sport->port.lock, flags);
1805 struct imx_port *sport = (struct imx_port *)port;
1807 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1815 struct imx_port *sport = (struct imx_port *)port;
1818 sport->port.type = PORT_IMX;
1829 struct imx_port *sport = (struct imx_port *)port;
1834 if (sport->port.irq != ser->irq)
1838 if (sport->port.uartclk / 16 != ser->baud_base)
1840 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1842 if (sport->port.iobase != ser->port)
1853 struct imx_port *sport = (struct imx_port *)port;
1858 retval = clk_prepare_enable(sport->clk_ipg);
1861 retval = clk_prepare_enable(sport->clk_per);
1863 clk_disable_unprepare(sport->clk_ipg);
1865 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1867 spin_lock_irqsave(&sport->port.lock, flags);
1876 ucr1 = imx_uart_readl(sport, UCR1);
1877 ucr2 = imx_uart_readl(sport, UCR2);
1879 if (imx_uart_is_imx1(sport))
1888 imx_uart_writel(sport, ucr1, UCR1);
1889 imx_uart_writel(sport, ucr2, UCR2);
1892 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1893 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1895 spin_unlock_irqrestore(&sport->port.lock, flags);
1902 struct imx_port *sport = (struct imx_port *)port;
1903 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1906 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
1911 struct imx_port *sport = (struct imx_port *)port;
1916 status = imx_uart_readl(sport, USR1);
1920 imx_uart_writel(sport, c, URTX0);
1924 status = imx_uart_readl(sport, USR2);
1933 struct imx_port *sport = (struct imx_port *)port;
1937 if (!sport->have_rtscts && !sport->have_rtsgpio)
1942 if (sport->have_rtscts && !sport->have_rtsgpio &&
1947 ucr2 = imx_uart_readl(sport, UCR2);
1949 imx_uart_rts_active(sport, &ucr2);
1951 imx_uart_rts_inactive(sport, &ucr2);
1952 imx_uart_writel(sport, ucr2, UCR2);
1993 struct imx_port *sport = (struct imx_port *)port;
1995 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
1998 imx_uart_writel(sport, ch, URTX0);
2007 struct imx_port *sport = imx_uart_ports[co->index];
2013 if (sport->port.sysrq)
2016 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2018 spin_lock_irqsave(&sport->port.lock, flags);
2023 imx_uart_ucrs_save(sport, &old_ucr);
2026 if (imx_uart_is_imx1(sport))
2031 imx_uart_writel(sport, ucr1, UCR1);
2033 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2035 uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
2041 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC));
2043 imx_uart_ucrs_restore(sport, &old_ucr);
2046 spin_unlock_irqrestore(&sport->port.lock, flags);
2054 imx_uart_console_get_options(struct imx_port *sport, int *baud,
2058 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
2064 ucr2 = imx_uart_readl(sport, UCR2);
2079 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
2080 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2082 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2088 uartclk = clk_get_rate(sport->clk_per);
2107 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2115 struct imx_port *sport;
2129 sport = imx_uart_ports[co->index];
2130 if (sport == NULL)
2134 retval = clk_prepare_enable(sport->clk_ipg);
2141 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2143 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2145 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2148 clk_disable_unprepare(sport->clk_ipg);
2152 retval = clk_prepare_enable(sport->clk_per);
2154 clk_disable_unprepare(sport->clk_ipg);
2192 static int imx_uart_probe_dt(struct imx_port *sport,
2198 sport->devdata = of_device_get_match_data(&pdev->dev);
2199 if (!sport->devdata)
2208 sport->port.line = ret;
2212 sport->have_rtscts = 1;
2215 sport->dte_mode = 1;
2218 sport->have_rtsgpio = 1;
2221 sport->inverted_tx = 1;
2224 sport->inverted_rx = 1;
2229 static inline int imx_uart_probe_dt(struct imx_port *sport,
2236 static void imx_uart_probe_pdata(struct imx_port *sport,
2241 sport->port.line = pdev->id;
2242 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
2248 sport->have_rtscts = 1;
2253 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx);
2256 spin_lock_irqsave(&sport->port.lock, flags);
2257 if (sport->tx_state == WAIT_AFTER_RTS)
2258 imx_uart_start_tx(&sport->port);
2259 spin_unlock_irqrestore(&sport->port.lock, flags);
2266 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx);
2269 spin_lock_irqsave(&sport->port.lock, flags);
2270 if (sport->tx_state == WAIT_AFTER_SEND)
2271 imx_uart_stop_tx(&sport->port);
2272 spin_unlock_irqrestore(&sport->port.lock, flags);
2279 struct imx_port *sport;
2286 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2287 if (!sport)
2290 ret = imx_uart_probe_dt(sport, pdev);
2292 imx_uart_probe_pdata(sport, pdev);
2296 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2298 sport->port.line);
2313 sport->port.dev = &pdev->dev;
2314 sport->port.mapbase = res->start;
2315 sport->port.membase = base;
2316 sport->port.type = PORT_IMX,
2317 sport->port.iotype = UPIO_MEM;
2318 sport->port.irq = rxirq;
2319 sport->port.fifosize = 32;
2320 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
2321 sport->port.ops = &imx_uart_pops;
2322 sport->port.rs485_config = imx_uart_rs485_config;
2323 sport->port.flags = UPF_BOOT_AUTOCONF;
2324 timer_setup(&sport->timer, imx_uart_timeout, 0);
2326 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2327 if (IS_ERR(sport->gpios))
2328 return PTR_ERR(sport->gpios);
2330 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2331 if (IS_ERR(sport->clk_ipg)) {
2332 ret = PTR_ERR(sport->clk_ipg);
2337 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2338 if (IS_ERR(sport->clk_per)) {
2339 ret = PTR_ERR(sport->clk_per);
2344 sport->port.uartclk = clk_get_rate(sport->clk_per);
2347 ret = clk_prepare_enable(sport->clk_ipg);
2354 sport->ucr1 = readl(sport->port.membase + UCR1);
2355 sport->ucr2 = readl(sport->port.membase + UCR2);
2356 sport->ucr3 = readl(sport->port.membase + UCR3);
2357 sport->ucr4 = readl(sport->port.membase + UCR4);
2358 sport->ufcr = readl(sport->port.membase + UFCR);
2360 ret = uart_get_rs485_mode(&sport->port);
2364 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2365 (!sport->have_rtscts && !sport->have_rtsgpio))
2373 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2374 sport->have_rtscts && !sport->have_rtsgpio &&
2375 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2376 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2381 ucr1 = imx_uart_readl(sport, UCR1);
2383 imx_uart_writel(sport, ucr1, UCR1);
2385 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2392 u32 ufcr = imx_uart_readl(sport, UFCR);
2394 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2401 imx_uart_writel(sport,
2407 u32 ufcr = imx_uart_readl(sport, UFCR);
2409 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2411 if (!imx_uart_is_imx1(sport))
2413 imx_uart_writel(sport, ucr3, UCR3);
2416 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2417 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2418 sport->trigger_start_tx.function = imx_trigger_start_tx;
2419 sport->trigger_stop_tx.function = imx_trigger_stop_tx;
2427 dev_name(&pdev->dev), sport);
2435 dev_name(&pdev->dev), sport);
2443 dev_name(&pdev->dev), sport);
2451 dev_name(&pdev->dev), sport);
2458 imx_uart_ports[sport->port.line] = sport;
2460 platform_set_drvdata(pdev, sport);
2462 ret = uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2465 clk_disable_unprepare(sport->clk_ipg);
2472 struct imx_port *sport = platform_get_drvdata(pdev);
2474 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2477 static void imx_uart_restore_context(struct imx_port *sport)
2481 spin_lock_irqsave(&sport->port.lock, flags);
2482 if (!sport->context_saved) {
2483 spin_unlock_irqrestore(&sport->port.lock, flags);
2487 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2488 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2489 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2490 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2491 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2492 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2493 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2494 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2495 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2496 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2497 sport->context_saved = false;
2498 spin_unlock_irqrestore(&sport->port.lock, flags);
2501 static void imx_uart_save_context(struct imx_port *sport)
2506 spin_lock_irqsave(&sport->port.lock, flags);
2507 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2508 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2509 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2510 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2511 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2512 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2513 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2514 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2515 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2516 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2517 sport->context_saved = true;
2518 spin_unlock_irqrestore(&sport->port.lock, flags);
2521 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2525 ucr3 = imx_uart_readl(sport, UCR3);
2527 imx_uart_writel(sport, USR1_AWAKE, USR1);
2532 imx_uart_writel(sport, ucr3, UCR3);
2534 if (sport->have_rtscts) {
2535 u32 ucr1 = imx_uart_readl(sport, UCR1);
2540 imx_uart_writel(sport, ucr1, UCR1);
2546 struct imx_port *sport = dev_get_drvdata(dev);
2548 imx_uart_save_context(sport);
2550 clk_disable(sport->clk_ipg);
2559 struct imx_port *sport = dev_get_drvdata(dev);
2564 ret = clk_enable(sport->clk_ipg);
2568 imx_uart_restore_context(sport);
2575 struct imx_port *sport = dev_get_drvdata(dev);
2578 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2579 disable_irq(sport->port.irq);
2581 ret = clk_prepare_enable(sport->clk_ipg);
2586 imx_uart_enable_wakeup(sport, true);
2593 struct imx_port *sport = dev_get_drvdata(dev);
2596 imx_uart_enable_wakeup(sport, false);
2598 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2599 enable_irq(sport->port.irq);
2601 clk_disable_unprepare(sport->clk_ipg);
2608 struct imx_port *sport = dev_get_drvdata(dev);
2610 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2612 return clk_prepare_enable(sport->clk_ipg);
2617 struct imx_port *sport = dev_get_drvdata(dev);
2619 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2621 clk_disable_unprepare(sport->clk_ipg);