Lines Matching refs:sport
314 static inline bool is_layerscape_lpuart(struct lpuart_port *sport)
316 return (sport->devtype == LS1021A_LPUART ||
317 sport->devtype == LS1028A_LPUART);
320 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport)
322 return sport->devtype == IMX8QXP_LPUART;
350 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en)
355 ret = clk_prepare_enable(sport->ipg_clk);
359 ret = clk_prepare_enable(sport->baud_clk);
361 clk_disable_unprepare(sport->ipg_clk);
365 clk_disable_unprepare(sport->baud_clk);
366 clk_disable_unprepare(sport->ipg_clk);
372 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport)
374 if (is_imx8qxp_lpuart(sport))
375 return clk_get_rate(sport->baud_clk);
377 return clk_get_rate(sport->ipg_clk);
417 static void lpuart_dma_tx(struct lpuart_port *sport)
419 struct circ_buf *xmit = &sport->port.state->xmit;
420 struct scatterlist *sgl = sport->tx_sgl;
421 struct device *dev = sport->port.dev;
422 struct dma_chan *chan = sport->dma_tx_chan;
425 if (sport->dma_tx_in_progress)
428 sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
431 sport->dma_tx_nents = 1;
432 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
434 sport->dma_tx_nents = 2;
441 ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents,
448 sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl,
451 if (!sport->dma_tx_desc) {
452 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
458 sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
459 sport->dma_tx_desc->callback_param = sport;
460 sport->dma_tx_in_progress = true;
461 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
472 struct lpuart_port *sport = arg;
473 struct scatterlist *sgl = &sport->tx_sgl[0];
474 struct circ_buf *xmit = &sport->port.state->xmit;
475 struct dma_chan *chan = sport->dma_tx_chan;
478 spin_lock_irqsave(&sport->port.lock, flags);
480 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
483 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
485 sport->port.icount.tx += sport->dma_tx_bytes;
486 sport->dma_tx_in_progress = false;
487 spin_unlock_irqrestore(&sport->port.lock, flags);
490 uart_write_wakeup(&sport->port);
492 if (waitqueue_active(&sport->dma_wait)) {
493 wake_up(&sport->dma_wait);
497 spin_lock_irqsave(&sport->port.lock, flags);
499 if (!lpuart_stopped_or_empty(&sport->port))
500 lpuart_dma_tx(sport);
502 spin_unlock_irqrestore(&sport->port.lock, flags);
505 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport)
507 switch (sport->port.iotype) {
509 return sport->port.mapbase + UARTDATA;
511 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1;
513 return sport->port.mapbase + UARTDR;
518 struct lpuart_port *sport = container_of(port,
523 dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport);
527 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
530 dev_err(sport->port.dev,
538 static bool lpuart_is_32(struct lpuart_port *sport)
540 return sport->port.iotype == UPIO_MEM32 ||
541 sport->port.iotype == UPIO_MEM32BE;
546 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
547 struct dma_chan *chan = sport->dma_tx_chan;
550 if (sport->lpuart_dma_tx_use) {
551 if (sport->dma_tx_in_progress) {
552 dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0],
553 sport->dma_tx_nents, DMA_TO_DEVICE);
554 sport->dma_tx_in_progress = false;
559 if (lpuart_is_32(sport)) {
560 val = lpuart32_read(&sport->port, UARTFIFO);
562 lpuart32_write(&sport->port, val, UARTFIFO);
564 val = readb(sport->port.membase + UARTCFIFO);
566 writeb(val, sport->port.membase + UARTCFIFO);
588 struct lpuart_port *sport = container_of(port,
593 sport->port.fifosize = 0;
595 spin_lock_irqsave(&sport->port.lock, flags);
597 writeb(0, sport->port.membase + UARTCR2);
599 temp = readb(sport->port.membase + UARTPFIFO);
602 sport->port.membase + UARTPFIFO);
606 sport->port.membase + UARTCFIFO);
609 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
610 readb(sport->port.membase + UARTDR);
611 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
614 writeb(0, sport->port.membase + UARTTWFIFO);
615 writeb(1, sport->port.membase + UARTRWFIFO);
618 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
619 spin_unlock_irqrestore(&sport->port.lock, flags);
642 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
645 sport->port.fifosize = 0;
647 spin_lock_irqsave(&sport->port.lock, flags);
650 lpuart32_write(&sport->port, 0, UARTCTRL);
652 temp = lpuart32_read(&sport->port, UARTFIFO);
655 lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO);
658 lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO);
661 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) {
662 lpuart32_read(&sport->port, UARTDATA);
663 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO);
667 lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL);
668 spin_unlock_irqrestore(&sport->port.lock, flags);
688 static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
690 struct circ_buf *xmit = &sport->port.state->xmit;
692 if (sport->port.x_char) {
693 writeb(sport->port.x_char, sport->port.membase + UARTDR);
694 sport->port.icount.tx++;
695 sport->port.x_char = 0;
699 if (lpuart_stopped_or_empty(&sport->port)) {
700 lpuart_stop_tx(&sport->port);
705 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
706 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
708 sport->port.icount.tx++;
712 uart_write_wakeup(&sport->port);
715 lpuart_stop_tx(&sport->port);
718 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
720 struct circ_buf *xmit = &sport->port.state->xmit;
723 if (sport->port.x_char) {
724 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
725 sport->port.icount.tx++;
726 sport->port.x_char = 0;
730 if (lpuart_stopped_or_empty(&sport->port)) {
731 lpuart32_stop_tx(&sport->port);
735 txcnt = lpuart32_read(&sport->port, UARTWATER);
738 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
739 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA);
741 sport->port.icount.tx++;
742 txcnt = lpuart32_read(&sport->port, UARTWATER);
748 uart_write_wakeup(&sport->port);
751 lpuart32_stop_tx(&sport->port);
756 struct lpuart_port *sport = container_of(port,
763 if (sport->lpuart_dma_tx_use) {
765 lpuart_dma_tx(sport);
768 lpuart_transmit_buffer(sport);
774 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
777 if (sport->lpuart_dma_tx_use) {
779 lpuart_dma_tx(sport);
785 lpuart32_transmit_buffer(sport);
792 struct lpuart_port *sport = container_of(port,
797 if (sport->dma_tx_in_progress)
808 struct lpuart_port *sport = container_of(port,
814 if (sport->dma_tx_in_progress)
828 static void lpuart_txint(struct lpuart_port *sport)
832 spin_lock_irqsave(&sport->port.lock, flags);
833 lpuart_transmit_buffer(sport);
834 spin_unlock_irqrestore(&sport->port.lock, flags);
837 static void lpuart_rxint(struct lpuart_port *sport)
840 struct tty_port *port = &sport->port.state->port;
844 spin_lock_irqsave(&sport->port.lock, flags);
846 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
848 sport->port.icount.rx++;
853 sr = readb(sport->port.membase + UARTSR1);
854 rx = readb(sport->port.membase + UARTDR);
856 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
861 sport->port.icount.parity++;
863 sport->port.icount.frame++;
868 if (sr & sport->port.ignore_status_mask) {
874 sr &= sport->port.read_status_mask;
884 sport->port.sysrq = 0;
892 sport->port.icount.overrun += overrun;
898 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
899 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO);
902 spin_unlock_irqrestore(&sport->port.lock, flags);
907 static void lpuart32_txint(struct lpuart_port *sport)
911 spin_lock_irqsave(&sport->port.lock, flags);
912 lpuart32_transmit_buffer(sport);
913 spin_unlock_irqrestore(&sport->port.lock, flags);
916 static void lpuart32_rxint(struct lpuart_port *sport)
919 struct tty_port *port = &sport->port.state->port;
923 spin_lock_irqsave(&sport->port.lock, flags);
925 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {
927 sport->port.icount.rx++;
932 sr = lpuart32_read(&sport->port, UARTSTAT);
933 rx = lpuart32_read(&sport->port, UARTDATA);
936 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
941 sport->port.icount.parity++;
943 sport->port.icount.frame++;
946 sport->port.icount.overrun++;
948 if (sr & sport->port.ignore_status_mask) {
954 sr &= sport->port.read_status_mask;
964 sport->port.sysrq = 0;
971 spin_unlock_irqrestore(&sport->port.lock, flags);
978 struct lpuart_port *sport = dev_id;
981 sts = readb(sport->port.membase + UARTSR1);
984 if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) {
985 readb(sport->port.membase + UARTDR);
986 uart_handle_break(&sport->port);
988 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
992 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use)
993 lpuart_rxint(sport);
995 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use)
996 lpuart_txint(sport);
1003 struct lpuart_port *sport = dev_id;
1006 sts = lpuart32_read(&sport->port, UARTSTAT);
1007 rxcount = lpuart32_read(&sport->port, UARTWATER);
1010 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use)
1011 lpuart32_rxint(sport);
1013 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use)
1014 lpuart32_txint(sport);
1016 lpuart32_write(&sport->port, sts, UARTSTAT);
1031 static void lpuart_handle_sysrq(struct lpuart_port *sport)
1033 struct circ_buf *ring = &sport->rx_ring;
1037 count = sport->rx_sgl.length - ring->tail;
1038 lpuart_handle_sysrq_chars(&sport->port,
1045 lpuart_handle_sysrq_chars(&sport->port,
1051 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
1053 struct tty_port *port = &sport->port.state->port;
1056 struct dma_chan *chan = sport->dma_rx_chan;
1057 struct circ_buf *ring = &sport->rx_ring;
1061 if (lpuart_is_32(sport)) {
1062 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT);
1066 lpuart32_write(&sport->port, sr, UARTSTAT);
1069 sport->port.icount.parity++;
1071 sport->port.icount.frame++;
1074 unsigned char sr = readb(sport->port.membase + UARTSR1);
1080 cr2 = readb(sport->port.membase + UARTCR2);
1082 writeb(cr2, sport->port.membase + UARTCR2);
1085 readb(sport->port.membase + UARTDR);
1088 sport->port.icount.parity++;
1090 sport->port.icount.frame++;
1100 if (readb(sport->port.membase + UARTSFIFO) &
1103 sport->port.membase + UARTSFIFO);
1105 sport->port.membase + UARTCFIFO);
1109 writeb(cr2, sport->port.membase + UARTCR2);
1113 async_tx_ack(sport->dma_rx_desc);
1115 spin_lock_irqsave(&sport->port.lock, flags);
1117 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);
1119 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
1120 spin_unlock_irqrestore(&sport->port.lock, flags);
1125 dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1,
1135 ring->head = sport->rx_sgl.length - state.residue;
1136 BUG_ON(ring->head > sport->rx_sgl.length);
1141 if (sport->port.sysrq) {
1142 lpuart_handle_sysrq(sport);
1149 * 0 <= ring->head <= sport->rx_sgl.length
1152 * 0 <= ring->tail <= sport->rx_sgl.length - 1
1159 count = sport->rx_sgl.length - ring->tail;
1163 sport->port.icount.rx += count;
1171 if (ring->head >= sport->rx_sgl.length)
1174 sport->port.icount.rx += count;
1178 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1,
1181 spin_unlock_irqrestore(&sport->port.lock, flags);
1184 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
1189 struct lpuart_port *sport = arg;
1191 lpuart_copy_rx_to_tty(sport);
1196 struct lpuart_port *sport = from_timer(sport, t, lpuart_timer);
1198 lpuart_copy_rx_to_tty(sport);
1201 static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
1204 struct circ_buf *ring = &sport->rx_ring;
1207 struct tty_port *port = &sport->port.state->port;
1210 struct dma_chan *chan = sport->dma_rx_chan;
1222 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2;
1223 sport->rx_dma_rng_buf_len = (1 << fls(sport->rx_dma_rng_buf_len));
1224 if (sport->rx_dma_rng_buf_len < 16)
1225 sport->rx_dma_rng_buf_len = 16;
1227 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
1231 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1232 nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1,
1236 dev_err(sport->port.dev, "DMA Rx mapping error\n");
1240 dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport);
1247 dev_err(sport->port.dev,
1252 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan,
1253 sg_dma_address(&sport->rx_sgl),
1254 sport->rx_sgl.length,
1255 sport->rx_sgl.length / 2,
1258 if (!sport->dma_rx_desc) {
1259 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
1263 sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
1264 sport->dma_rx_desc->callback_param = sport;
1265 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
1268 if (lpuart_is_32(sport)) {
1269 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD);
1271 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD);
1273 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
1274 sport->port.membase + UARTCR5);
1282 struct lpuart_port *sport = container_of(port,
1284 struct dma_chan *chan = sport->dma_rx_chan;
1287 del_timer_sync(&sport->lpuart_timer);
1288 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1289 kfree(sport->rx_ring.buf);
1290 sport->rx_ring.tail = 0;
1291 sport->rx_ring.head = 0;
1292 sport->dma_rx_desc = NULL;
1293 sport->dma_rx_cookie = -EINVAL;
1299 struct lpuart_port *sport = container_of(port,
1302 u8 modem = readb(sport->port.membase + UARTMODEM) &
1304 writeb(modem, sport->port.membase + UARTMODEM);
1341 sport->port.rs485 = *rs485;
1343 writeb(modem, sport->port.membase + UARTMODEM);
1350 struct lpuart_port *sport = container_of(port,
1353 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR)
1355 lpuart32_write(&sport->port, modem, UARTMODIR);
1392 sport->port.rs485 = *rs485;
1394 lpuart32_write(&sport->port, modem, UARTMODIR);
1421 struct lpuart_port *sport = container_of(port,
1425 if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) {
1426 temp = readb(sport->port.membase + UARTMODEM) &
1490 static void lpuart_setup_watermark(struct lpuart_port *sport)
1495 cr2 = readb(sport->port.membase + UARTCR2);
1499 writeb(cr2, sport->port.membase + UARTCR2);
1501 val = readb(sport->port.membase + UARTPFIFO);
1503 sport->port.membase + UARTPFIFO);
1507 sport->port.membase + UARTCFIFO);
1510 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1511 readb(sport->port.membase + UARTDR);
1512 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1515 writeb(0, sport->port.membase + UARTTWFIFO);
1516 writeb(1, sport->port.membase + UARTRWFIFO);
1519 writeb(cr2_saved, sport->port.membase + UARTCR2);
1522 static void lpuart_setup_watermark_enable(struct lpuart_port *sport)
1526 lpuart_setup_watermark(sport);
1528 cr2 = readb(sport->port.membase + UARTCR2);
1530 writeb(cr2, sport->port.membase + UARTCR2);
1533 static void lpuart32_setup_watermark(struct lpuart_port *sport)
1538 ctrl = lpuart32_read(&sport->port, UARTCTRL);
1542 lpuart32_write(&sport->port, ctrl, UARTCTRL);
1545 val = lpuart32_read(&sport->port, UARTFIFO);
1548 lpuart32_write(&sport->port, val, UARTFIFO);
1552 lpuart32_write(&sport->port, val, UARTWATER);
1555 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
1558 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport)
1562 lpuart32_setup_watermark(sport);
1564 temp = lpuart32_read(&sport->port, UARTCTRL);
1566 lpuart32_write(&sport->port, temp, UARTCTRL);
1569 static void rx_dma_timer_init(struct lpuart_port *sport)
1571 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0);
1572 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1573 add_timer(&sport->lpuart_timer);
1576 static void lpuart_request_dma(struct lpuart_port *sport)
1578 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx");
1579 if (IS_ERR(sport->dma_tx_chan)) {
1580 dev_dbg_once(sport->port.dev,
1582 PTR_ERR(sport->dma_tx_chan));
1583 sport->dma_tx_chan = NULL;
1586 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx");
1587 if (IS_ERR(sport->dma_rx_chan)) {
1588 dev_dbg_once(sport->port.dev,
1590 PTR_ERR(sport->dma_rx_chan));
1591 sport->dma_rx_chan = NULL;
1595 static void lpuart_tx_dma_startup(struct lpuart_port *sport)
1600 if (uart_console(&sport->port))
1603 if (!sport->dma_tx_chan)
1606 ret = lpuart_dma_tx_request(&sport->port);
1610 init_waitqueue_head(&sport->dma_wait);
1611 sport->lpuart_dma_tx_use = true;
1612 if (lpuart_is_32(sport)) {
1613 uartbaud = lpuart32_read(&sport->port, UARTBAUD);
1614 lpuart32_write(&sport->port,
1617 writeb(readb(sport->port.membase + UARTCR5) |
1618 UARTCR5_TDMAS, sport->port.membase + UARTCR5);
1624 sport->lpuart_dma_tx_use = false;
1627 static void lpuart_rx_dma_startup(struct lpuart_port *sport)
1632 if (uart_console(&sport->port))
1635 if (!sport->dma_rx_chan)
1638 ret = lpuart_start_rx_dma(sport);
1643 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1644 if (!sport->dma_rx_timeout)
1645 sport->dma_rx_timeout = 1;
1647 sport->lpuart_dma_rx_use = true;
1648 rx_dma_timer_init(sport);
1650 if (sport->port.has_sysrq && !lpuart_is_32(sport)) {
1651 cr3 = readb(sport->port.membase + UARTCR3);
1653 writeb(cr3, sport->port.membase + UARTCR3);
1659 sport->lpuart_dma_rx_use = false;
1664 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1669 temp = readb(sport->port.membase + UARTPFIFO);
1671 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) &
1673 sport->port.fifosize = sport->txfifo_size;
1675 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) &
1678 lpuart_request_dma(sport);
1680 spin_lock_irqsave(&sport->port.lock, flags);
1682 lpuart_setup_watermark_enable(sport);
1684 lpuart_rx_dma_startup(sport);
1685 lpuart_tx_dma_startup(sport);
1687 spin_unlock_irqrestore(&sport->port.lock, flags);
1692 static void lpuart32_configure(struct lpuart_port *sport)
1696 if (sport->lpuart_dma_rx_use) {
1698 temp = lpuart32_read(&sport->port, UARTWATER);
1700 lpuart32_write(&sport->port, temp, UARTWATER);
1702 temp = lpuart32_read(&sport->port, UARTCTRL);
1703 if (!sport->lpuart_dma_rx_use)
1705 if (!sport->lpuart_dma_tx_use)
1707 lpuart32_write(&sport->port, temp, UARTCTRL);
1712 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1717 temp = lpuart32_read(&sport->port, UARTFIFO);
1719 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) &
1721 sport->port.fifosize = sport->txfifo_size;
1723 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) &
1731 if (is_layerscape_lpuart(sport)) {
1732 sport->rxfifo_size = 16;
1733 sport->txfifo_size = 16;
1734 sport->port.fifosize = sport->txfifo_size;
1737 lpuart_request_dma(sport);
1739 spin_lock_irqsave(&sport->port.lock, flags);
1741 lpuart32_setup_watermark_enable(sport);
1743 lpuart_rx_dma_startup(sport);
1744 lpuart_tx_dma_startup(sport);
1746 lpuart32_configure(sport);
1748 spin_unlock_irqrestore(&sport->port.lock, flags);
1752 static void lpuart_dma_shutdown(struct lpuart_port *sport)
1754 if (sport->lpuart_dma_rx_use) {
1755 lpuart_dma_rx_free(&sport->port);
1756 sport->lpuart_dma_rx_use = false;
1759 if (sport->lpuart_dma_tx_use) {
1760 if (wait_event_interruptible(sport->dma_wait,
1761 !sport->dma_tx_in_progress) != false) {
1762 sport->dma_tx_in_progress = false;
1763 dmaengine_terminate_all(sport->dma_tx_chan);
1765 sport->lpuart_dma_tx_use = false;
1768 if (sport->dma_tx_chan)
1769 dma_release_channel(sport->dma_tx_chan);
1770 if (sport->dma_rx_chan)
1771 dma_release_channel(sport->dma_rx_chan);
1776 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1790 lpuart_dma_shutdown(sport);
1795 struct lpuart_port *sport =
1810 lpuart_dma_shutdown(sport);
1817 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1824 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1825 old_cr2 = readb(sport->port.membase + UARTCR2);
1826 cr3 = readb(sport->port.membase + UARTCR3);
1827 cr4 = readb(sport->port.membase + UARTCR4);
1828 bdh = readb(sport->port.membase + UARTBDH);
1829 modem = readb(sport->port.membase + UARTMODEM);
1861 if (sport->port.rs485.flags & SER_RS485_ENABLED)
1902 * Since timer function acqures sport->port.lock, need to stop before
1905 if (old && sport->lpuart_dma_rx_use)
1906 lpuart_dma_rx_free(&sport->port);
1908 spin_lock_irqsave(&sport->port.lock, flags);
1910 sport->port.read_status_mask = 0;
1912 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE;
1914 sport->port.read_status_mask |= UARTSR1_FE;
1917 sport->port.ignore_status_mask = 0;
1919 sport->port.ignore_status_mask |= UARTSR1_PE;
1921 sport->port.ignore_status_mask |= UARTSR1_FE;
1927 sport->port.ignore_status_mask |= UARTSR1_OR;
1934 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
1938 sport->port.membase + UARTCR2);
1940 sbr = sport->port.uartclk / (16 * baud);
1941 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1946 writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1947 writeb(bdh, sport->port.membase + UARTBDH);
1948 writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
1949 writeb(cr3, sport->port.membase + UARTCR3);
1950 writeb(cr1, sport->port.membase + UARTCR1);
1951 writeb(modem, sport->port.membase + UARTMODEM);
1954 writeb(old_cr2, sport->port.membase + UARTCR2);
1956 if (old && sport->lpuart_dma_rx_use) {
1957 if (!lpuart_start_rx_dma(sport))
1958 rx_dma_timer_init(sport);
1960 sport->lpuart_dma_rx_use = false;
1963 spin_unlock_irqrestore(&sport->port.lock, flags);
2042 static void lpuart32_serial_setbrg(struct lpuart_port *sport,
2045 __lpuart32_serial_setbrg(&sport->port, baudrate,
2046 sport->lpuart_dma_rx_use,
2047 sport->lpuart_dma_tx_use);
2055 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
2061 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
2062 modem = lpuart32_read(&sport->port, UARTMODIR);
2094 if (sport->port.rs485.flags & SER_RS485_ENABLED)
2135 * Since timer function acqures sport->port.lock, need to stop before
2138 if (old && sport->lpuart_dma_rx_use)
2139 lpuart_dma_rx_free(&sport->port);
2141 spin_lock_irqsave(&sport->port.lock, flags);
2143 sport->port.read_status_mask = 0;
2145 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE;
2147 sport->port.read_status_mask |= UARTSTAT_FE;
2150 sport->port.ignore_status_mask = 0;
2152 sport->port.ignore_status_mask |= UARTSTAT_PE;
2154 sport->port.ignore_status_mask |= UARTSTAT_FE;
2160 sport->port.ignore_status_mask |= UARTSTAT_OR;
2172 lpuart32_write(&sport->port, 0, UARTMODIR);
2173 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2177 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
2180 lpuart32_serial_setbrg(sport, baud);
2181 lpuart32_write(&sport->port, modem, UARTMODIR);
2182 lpuart32_write(&sport->port, ctrl, UARTCTRL);
2185 if (old && sport->lpuart_dma_rx_use) {
2186 if (!lpuart_start_rx_dma(sport))
2187 rx_dma_timer_init(sport);
2189 sport->lpuart_dma_rx_use = false;
2192 spin_unlock_irqrestore(&sport->port.lock, flags);
2302 struct lpuart_port *sport = lpuart_ports[co->index];
2307 if (sport->port.sysrq || oops_in_progress)
2308 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2310 spin_lock_irqsave(&sport->port.lock, flags);
2313 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
2316 writeb(cr2, sport->port.membase + UARTCR2);
2318 uart_console_write(&sport->port, s, count, lpuart_console_putchar);
2321 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
2323 writeb(old_cr2, sport->port.membase + UARTCR2);
2326 spin_unlock_irqrestore(&sport->port.lock, flags);
2332 struct lpuart_port *sport = lpuart_ports[co->index];
2337 if (sport->port.sysrq || oops_in_progress)
2338 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2340 spin_lock_irqsave(&sport->port.lock, flags);
2343 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
2346 lpuart32_write(&sport->port, cr, UARTCTRL);
2348 uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
2351 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2353 lpuart32_write(&sport->port, old_cr, UARTCTRL);
2356 spin_unlock_irqrestore(&sport->port.lock, flags);
2364 lpuart_console_get_options(struct lpuart_port *sport, int *baud,
2370 cr = readb(sport->port.membase + UARTCR2);
2377 cr = readb(sport->port.membase + UARTCR1);
2392 bdh = readb(sport->port.membase + UARTBDH);
2394 bdl = readb(sport->port.membase + UARTBDL);
2398 brfa = readb(sport->port.membase + UARTCR4);
2401 uartclk = lpuart_get_baud_clk_rate(sport);
2408 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2413 lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
2419 cr = lpuart32_read(&sport->port, UARTCTRL);
2426 cr = lpuart32_read(&sport->port, UARTCTRL);
2441 bd = lpuart32_read(&sport->port, UARTBAUD);
2447 uartclk = lpuart_get_baud_clk_rate(sport);
2454 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2460 struct lpuart_port *sport;
2474 sport = lpuart_ports[co->index];
2475 if (sport == NULL)
2481 if (lpuart_is_32(sport))
2482 lpuart32_console_get_options(sport, &baud, &parity, &bits);
2484 lpuart_console_get_options(sport, &baud, &parity, &bits);
2486 if (lpuart_is_32(sport))
2487 lpuart32_setup_watermark(sport);
2489 lpuart_setup_watermark(sport);
2491 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
2618 struct lpuart_port *sport;
2623 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2624 if (!sport)
2628 sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
2629 if (IS_ERR(sport->port.membase))
2630 return PTR_ERR(sport->port.membase);
2632 sport->port.membase += sdata->reg_off;
2633 sport->port.mapbase = res->start + sdata->reg_off;
2634 sport->port.dev = &pdev->dev;
2635 sport->port.type = PORT_LPUART;
2636 sport->devtype = sdata->devtype;
2640 sport->port.irq = ret;
2641 sport->port.iotype = sdata->iotype;
2642 if (lpuart_is_32(sport))
2643 sport->port.ops = &lpuart32_pops;
2645 sport->port.ops = &lpuart_pops;
2646 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE);
2647 sport->port.flags = UPF_BOOT_AUTOCONF;
2649 if (lpuart_is_32(sport))
2650 sport->port.rs485_config = lpuart32_config_rs485;
2652 sport->port.rs485_config = lpuart_config_rs485;
2654 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
2655 if (IS_ERR(sport->ipg_clk)) {
2656 ret = PTR_ERR(sport->ipg_clk);
2661 sport->baud_clk = NULL;
2662 if (is_imx8qxp_lpuart(sport)) {
2663 sport->baud_clk = devm_clk_get(&pdev->dev, "baud");
2664 if (IS_ERR(sport->baud_clk)) {
2665 ret = PTR_ERR(sport->baud_clk);
2680 sport->port.line = ret;
2682 ret = lpuart_enable_clks(sport);
2685 sport->port.uartclk = lpuart_get_baud_clk_rate(sport);
2687 lpuart_ports[sport->port.line] = sport;
2689 platform_set_drvdata(pdev, &sport->port);
2691 if (lpuart_is_32(sport)) {
2699 ret = uart_get_rs485_mode(&sport->port);
2703 if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX)
2706 if (sport->port.rs485.delay_rts_before_send ||
2707 sport->port.rs485.delay_rts_after_send)
2710 ret = uart_add_one_port(&lpuart_reg, &sport->port);
2714 ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0,
2715 DRIVER_NAME, sport);
2722 uart_remove_one_port(&lpuart_reg, &sport->port);
2725 lpuart_disable_clks(sport);
2731 struct lpuart_port *sport = platform_get_drvdata(pdev);
2733 uart_remove_one_port(&lpuart_reg, &sport->port);
2735 lpuart_disable_clks(sport);
2737 if (sport->dma_tx_chan)
2738 dma_release_channel(sport->dma_tx_chan);
2740 if (sport->dma_rx_chan)
2741 dma_release_channel(sport->dma_rx_chan);
2748 struct lpuart_port *sport = dev_get_drvdata(dev);
2752 if (lpuart_is_32(sport)) {
2754 temp = lpuart32_read(&sport->port, UARTCTRL);
2756 lpuart32_write(&sport->port, temp, UARTCTRL);
2759 temp = readb(sport->port.membase + UARTCR2);
2761 writeb(temp, sport->port.membase + UARTCR2);
2764 uart_suspend_port(&lpuart_reg, &sport->port);
2767 irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2769 if (sport->lpuart_dma_rx_use) {
2778 lpuart_dma_rx_free(&sport->port);
2782 if (lpuart_is_32(sport)) {
2783 temp = lpuart32_read(&sport->port, UARTBAUD);
2784 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE,
2787 writeb(readb(sport->port.membase + UARTCR5) &
2788 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
2792 if (sport->lpuart_dma_tx_use) {
2793 sport->dma_tx_in_progress = false;
2794 dmaengine_terminate_all(sport->dma_tx_chan);
2797 if (sport->port.suspended && !irq_wake)
2798 lpuart_disable_clks(sport);
2805 struct lpuart_port *sport = dev_get_drvdata(dev);
2806 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2808 if (sport->port.suspended && !irq_wake)
2809 lpuart_enable_clks(sport);
2811 if (lpuart_is_32(sport))
2812 lpuart32_setup_watermark_enable(sport);
2814 lpuart_setup_watermark_enable(sport);
2816 if (sport->lpuart_dma_rx_use) {
2818 if (!lpuart_start_rx_dma(sport))
2819 rx_dma_timer_init(sport);
2821 sport->lpuart_dma_rx_use = false;
2825 lpuart_tx_dma_startup(sport);
2827 if (lpuart_is_32(sport))
2828 lpuart32_configure(sport);
2830 uart_resume_port(&lpuart_reg, &sport->port);