Lines Matching refs:status
24 #define LINSR 0x0008 /* LIN status register */
25 #define LINESR 0x000C /* LIN error status register */
27 #define UARTSR 0x0014 /* UART mode status register */
28 #define LINTCSR 0x0018 /* LIN timeout control status register */
164 unsigned long status;
171 while (((status = readl(sport->membase + UARTSR)) &
179 writel(status | LINFLEXD_UARTSR_DTFTFF,
204 unsigned long status;
212 while (((status = readl(sport->membase + UARTSR)) &
216 writel(status | LINFLEXD_UARTSR_DTFTFF,
242 unsigned long flags, status;
248 status = readl(sport->membase + UARTSR);
249 while (status & LINFLEXD_UARTSR_RMB) {
255 if (status & (LINFLEXD_UARTSR_BOF | LINFLEXD_UARTSR_SZF |
257 if (status & LINFLEXD_UARTSR_SZF)
258 status |= LINFLEXD_UARTSR_SZF;
259 if (status & LINFLEXD_UARTSR_BOF)
260 status |= LINFLEXD_UARTSR_BOF;
261 if (status & LINFLEXD_UARTSR_FEF) {
264 status |= LINFLEXD_UARTSR_FEF;
266 if (status & LINFLEXD_UARTSR_PE)
267 status |= LINFLEXD_UARTSR_PE;
270 writel(status | LINFLEXD_UARTSR_RMB | LINFLEXD_UARTSR_DRFRFE,
272 status = readl(sport->membase + UARTSR);
293 unsigned long status;
295 status = readl(sport->membase + UARTSR);
297 if (status & LINFLEXD_UARTSR_DRFRFE)
299 if (status & LINFLEXD_UARTSR_DTFTFF)
308 unsigned long status;
310 status = readl(port->membase + UARTSR) & LINFLEXD_UARTSR_DTFTFF;
312 return status ? TIOCSER_TEMT : 0;