Lines Matching defs:port
77 struct uart_port *port = &device->port;
79 if (port->iotype == UPIO_MEM || port->iotype == UPIO_MEM16 ||
80 port->iotype == UPIO_MEM32 || port->iotype == UPIO_MEM32BE)
83 (port->iotype == UPIO_MEM) ? "" :
84 (port->iotype == UPIO_MEM16) ? "16" :
85 (port->iotype == UPIO_MEM32) ? "32" : "32be",
86 &port->mapbase, device->options);
88 pr_info("%s%d at I/O port 0x%lx (options '%s')\n",
90 port->iobase, device->options);
95 struct uart_port *port = &device->port;
99 if (uart_parse_earlycon(options, &port->iotype, &addr, &options))
102 switch (port->iotype) {
104 port->mapbase = addr;
107 port->regshift = 1;
108 port->mapbase = addr;
112 port->regshift = 2;
113 port->mapbase = addr;
116 port->iobase = addr;
135 struct uart_port *port = &early_console_dev.port;
141 spin_lock_init(&port->lock);
142 port->uartclk = BASE_BAUD * 16;
143 if (port->mapbase)
144 port->membase = earlycon_map(port->mapbase, 64);
253 struct uart_port *port = &early_console_dev.port;
258 spin_lock_init(&port->lock);
259 port->iotype = UPIO_MEM;
265 port->mapbase = addr;
269 port->mapbase += be32_to_cpu(*val);
270 port->membase = earlycon_map(port->mapbase, SZ_4K);
274 port->regshift = be32_to_cpu(*val);
282 port->iotype = UPIO_MEM;
285 port->iotype = UPIO_MEM16;
288 port->iotype = (big_endian) ? UPIO_MEM32BE : UPIO_MEM32;
302 port->uartclk = be32_to_cpu(*val);