Lines Matching refs:atmel_port
235 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
237 return atmel_port->use_pdc_rx;
242 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
244 return atmel_port->use_pdc_tx;
260 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
262 return atmel_port->use_dma_tx;
267 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
269 return atmel_port->use_dma_rx;
274 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
276 return atmel_port->fifo_size;
279 static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
282 if (!atomic_read(&atmel_port->tasklet_shutdown))
290 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
294 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
301 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
303 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
312 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
315 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
320 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
328 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
332 mck_rate = (u64)clk_get_rate(atmel_port->clk);
355 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
361 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
399 } else if (fidi < atmel_port->fidi_min
400 || fidi > atmel_port->fidi_max) {
409 atmel_port->backup_mode = atmel_uart_readl(port, ATMEL_US_MR);
410 atmel_port->backup_brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
418 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY | ATMEL_US_NACK | ATMEL_US_ITERATION;
422 mode = atmel_port->backup_mode;
425 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->backup_brgr);
429 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
432 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
441 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
451 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
453 if (atmel_port->tx_stopped)
468 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
505 mctrl_gpio_set(atmel_port->gpios, mctrl);
522 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
539 return mctrl_gpio_get(atmel_port->gpios, &ret);
547 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
560 atmel_port->tx_stopped = true;
563 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
566 if (!atomic_read(&atmel_port->tasklet_shutdown))
576 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
593 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
597 atmel_port->tx_stopped = false;
644 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
650 if (atmel_port->ms_irq_enabled)
653 atmel_port->ms_irq_enabled = true;
655 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
658 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
661 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
664 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
669 mctrl_gpio_enable_ms(atmel_port->gpios);
677 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
683 if (!atmel_port->ms_irq_enabled)
686 atmel_port->ms_irq_enabled = false;
688 mctrl_gpio_disable_ms(atmel_port->gpios);
690 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
693 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
696 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
699 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
725 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
726 struct circ_buf *ring = &atmel_port->rx_ring;
769 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
782 || atmel_port->break_active)) {
788 && !atmel_port->break_active) {
789 atmel_port->break_active = 1;
803 atmel_port->break_active = 0;
811 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
821 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
848 atmel_port->tx_done_mask |= ATMEL_US_TXRDY;
852 atmel_port->tx_done_mask);
855 atmel_port->tx_done_mask &= ~ATMEL_US_TXRDY;
861 struct atmel_uart_port *atmel_port = arg;
862 struct uart_port *port = &atmel_port->uart;
864 struct dma_chan *chan = atmel_port->chan_tx;
871 xmit->tail += atmel_port->tx_len;
874 port->icount.tx += atmel_port->tx_len;
876 spin_lock(&atmel_port->lock_tx);
877 async_tx_ack(atmel_port->desc_tx);
878 atmel_port->cookie_tx = -EINVAL;
879 atmel_port->desc_tx = NULL;
880 spin_unlock(&atmel_port->lock_tx);
891 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
897 atmel_port->hd_start_rx = true;
899 atmel_port->tx_done_mask);
907 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
908 struct dma_chan *chan = atmel_port->chan_tx;
913 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
917 atmel_port->desc_tx = NULL;
918 atmel_port->chan_tx = NULL;
919 atmel_port->cookie_tx = -EINVAL;
927 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
929 struct dma_chan *chan = atmel_port->chan_tx;
931 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
936 if (atmel_port->desc_tx != NULL)
953 if (atmel_port->fifo_size) {
984 atmel_port->tx_len = tx_len;
999 atmel_port->desc_tx = desc;
1001 desc->callback_param = atmel_port;
1002 atmel_port->cookie_tx = dmaengine_submit(desc);
1003 if (dma_submit_error(atmel_port->cookie_tx)) {
1005 atmel_port->cookie_tx);
1018 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1027 atmel_port->chan_tx = dma_request_slave_channel(mfd_dev, "tx");
1028 if (atmel_port->chan_tx == NULL)
1031 dma_chan_name(atmel_port->chan_tx));
1033 spin_lock_init(&atmel_port->lock_tx);
1034 sg_init_table(&atmel_port->sg_tx, 1);
1037 sg_set_page(&atmel_port->sg_tx,
1042 &atmel_port->sg_tx,
1051 sg_dma_len(&atmel_port->sg_tx),
1053 &sg_dma_address(&atmel_port->sg_tx));
1059 config.dst_addr_width = (atmel_port->fifo_size) ?
1065 ret = dmaengine_slave_config(atmel_port->chan_tx,
1076 atmel_port->use_dma_tx = false;
1077 if (atmel_port->chan_tx)
1085 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1087 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1092 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1093 struct dma_chan *chan = atmel_port->chan_rx;
1098 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1102 atmel_port->desc_rx = NULL;
1103 atmel_port->chan_rx = NULL;
1104 atmel_port->cookie_rx = -EINVAL;
1109 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1111 struct circ_buf *ring = &atmel_port->rx_ring;
1112 struct dma_chan *chan = atmel_port->chan_rx;
1121 atmel_port->cookie_rx,
1127 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1133 &atmel_port->sg_rx,
1144 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1145 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1149 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1152 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1159 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1172 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1180 &atmel_port->sg_rx,
1197 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1205 ring = &atmel_port->rx_ring;
1210 atmel_port->chan_rx = dma_request_slave_channel(mfd_dev, "rx");
1211 if (atmel_port->chan_rx == NULL)
1214 dma_chan_name(atmel_port->chan_rx));
1216 spin_lock_init(&atmel_port->lock_rx);
1217 sg_init_table(&atmel_port->sg_rx, 1);
1220 sg_set_page(&atmel_port->sg_rx,
1225 &atmel_port->sg_rx,
1234 sg_dma_len(&atmel_port->sg_rx),
1236 &sg_dma_address(&atmel_port->sg_rx));
1246 ret = dmaengine_slave_config(atmel_port->chan_rx,
1256 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1257 sg_dma_address(&atmel_port->sg_rx),
1258 sg_dma_len(&atmel_port->sg_rx),
1259 sg_dma_len(&atmel_port->sg_rx)/2,
1268 atmel_port->desc_rx = desc;
1269 atmel_port->cookie_rx = dmaengine_submit(desc);
1270 if (dma_submit_error(atmel_port->cookie_rx)) {
1272 atmel_port->cookie_rx);
1276 dma_async_issue_pending(atmel_port->chan_rx);
1282 atmel_port->use_dma_rx = false;
1283 if (atmel_port->chan_rx)
1290 struct atmel_uart_port *atmel_port = from_timer(atmel_port, t,
1292 struct uart_port *port = &atmel_port->uart;
1294 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1295 tasklet_schedule(&atmel_port->tasklet_rx);
1296 mod_timer(&atmel_port->uart_timer,
1307 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1320 atmel_tasklet_schedule(atmel_port,
1321 &atmel_port->tasklet_rx);
1333 atmel_tasklet_schedule(atmel_port,
1334 &atmel_port->tasklet_rx);
1348 atmel_port->break_active = 0;
1358 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1360 if (pending & atmel_port->tx_done_mask) {
1362 atmel_port->tx_done_mask);
1365 if (atmel_port->hd_start_rx) {
1370 atmel_port->hd_start_rx = false;
1374 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1385 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1390 status_change = status ^ atmel_port->irq_status_prev;
1391 atmel_port->irq_status_prev = status;
1419 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1422 spin_lock(&atmel_port->lock_suspended);
1431 if (atmel_port->suspended) {
1432 atmel_port->pending |= pending;
1433 atmel_port->pending_status = status;
1444 spin_unlock(&atmel_port->lock_suspended);
1451 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1452 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1465 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1467 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1501 atmel_port->tx_done_mask);
1515 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1516 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1532 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1533 struct circ_buf *ring = &atmel_port->rx_ring;
1600 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1604 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1616 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1619 int rx_idx = atmel_port->pdc_rx_idx;
1628 pdc = &atmel_port->pdc_rx[rx_idx];
1676 atmel_port->pdc_rx_idx = rx_idx;
1694 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1698 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1704 atmel_port->pdc_rx[0].dma_addr,
1707 kfree(atmel_port->pdc_rx[0].buf);
1709 atmel_port->use_pdc_rx = false;
1720 atmel_port->pdc_rx_idx = 0;
1722 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1726 atmel_port->pdc_rx[1].dma_addr);
1737 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
1739 struct uart_port *port = &atmel_port->uart;
1743 atmel_port->schedule_rx(port);
1749 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
1751 struct uart_port *port = &atmel_port->uart;
1755 atmel_port->schedule_tx(port);
1759 static void atmel_init_property(struct atmel_uart_port *atmel_port,
1767 atmel_port->use_dma_rx = true;
1768 atmel_port->use_pdc_rx = false;
1770 atmel_port->use_dma_rx = false;
1771 atmel_port->use_pdc_rx = true;
1774 atmel_port->use_dma_rx = false;
1775 atmel_port->use_pdc_rx = false;
1780 atmel_port->use_dma_tx = true;
1781 atmel_port->use_pdc_tx = false;
1783 atmel_port->use_dma_tx = false;
1784 atmel_port->use_pdc_tx = true;
1787 atmel_port->use_dma_tx = false;
1788 atmel_port->use_pdc_tx = false;
1794 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1797 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1798 atmel_port->schedule_rx = &atmel_rx_from_dma;
1799 atmel_port->release_rx = &atmel_release_rx_dma;
1801 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1802 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1803 atmel_port->release_rx = &atmel_release_rx_pdc;
1805 atmel_port->prepare_rx = NULL;
1806 atmel_port->schedule_rx = &atmel_rx_from_ring;
1807 atmel_port->release_rx = NULL;
1811 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1812 atmel_port->schedule_tx = &atmel_tx_dma;
1813 atmel_port->release_tx = &atmel_release_tx_dma;
1815 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1816 atmel_port->schedule_tx = &atmel_tx_pdc;
1817 atmel_port->release_tx = &atmel_release_tx_pdc;
1819 atmel_port->prepare_tx = NULL;
1820 atmel_port->schedule_tx = &atmel_tx_chars;
1821 atmel_port->release_tx = NULL;
1830 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1845 atmel_port->has_frac_baudrate = false;
1846 atmel_port->has_hw_timer = false;
1850 atmel_port->has_hw_timer = true;
1851 atmel_port->rtor = ATMEL_UA_RTOR;
1854 atmel_port->has_frac_baudrate = true;
1855 atmel_port->has_hw_timer = true;
1856 atmel_port->rtor = ATMEL_US_RTOR;
1862 atmel_port->fidi_min = 3;
1863 atmel_port->fidi_max = 65535;
1866 atmel_port->fidi_min = 3;
1867 atmel_port->fidi_max = 2047;
1870 atmel_port->fidi_min = 1;
1871 atmel_port->fidi_max = 2047;
1883 atmel_port->has_frac_baudrate = true;
1884 atmel_port->has_hw_timer = true;
1885 atmel_port->rtor = ATMEL_US_RTOR;
1903 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1912 atmel_port->ms_irq_enabled = false;
1925 atomic_set(&atmel_port->tasklet_shutdown, 0);
1926 tasklet_setup(&atmel_port->tasklet_rx, atmel_tasklet_rx_func);
1927 tasklet_setup(&atmel_port->tasklet_tx, atmel_tasklet_tx_func);
1932 atmel_init_property(atmel_port, pdev);
1935 if (atmel_port->prepare_rx) {
1936 retval = atmel_port->prepare_rx(port);
1941 if (atmel_port->prepare_tx) {
1942 retval = atmel_port->prepare_tx(port);
1950 if (atmel_port->fifo_size) {
1964 if (atmel_port->rts_high &&
1965 atmel_port->rts_low)
1967 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1968 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1974 atmel_port->irq_status_prev = atmel_uart_readl(port, ATMEL_US_CSR);
1982 atmel_port->tx_stopped = false;
1984 timer_setup(&atmel_port->uart_timer, atmel_uart_timer_callback, 0);
1988 if (!atmel_port->has_hw_timer) {
1989 mod_timer(&atmel_port->uart_timer,
1993 atmel_uart_writel(port, atmel_port->rtor,
2004 if (!atmel_port->has_hw_timer) {
2005 mod_timer(&atmel_port->uart_timer,
2009 atmel_uart_writel(port, atmel_port->rtor,
2030 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2034 atmel_port->pdc_tx.ofs = 0;
2040 atmel_port->tx_len = 0;
2048 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2057 atomic_inc(&atmel_port->tasklet_shutdown);
2063 del_timer_sync(&atmel_port->uart_timer);
2072 tasklet_kill(&atmel_port->tasklet_rx);
2073 tasklet_kill(&atmel_port->tasklet_tx);
2087 if (atmel_port->release_rx)
2088 atmel_port->release_rx(port);
2089 if (atmel_port->release_tx)
2090 atmel_port->release_tx(port);
2095 atmel_port->rx_ring.head = 0;
2096 atmel_port->rx_ring.tail = 0;
2112 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2120 clk_prepare_enable(atmel_port->clk);
2123 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2127 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2134 clk_disable_unprepare(atmel_port->clk);
2147 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2237 atmel_port->tx_stopped = true;
2258 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2296 if (atmel_port->has_frac_baudrate) {
2336 atmel_port->tx_stopped = false;
2494 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2498 struct uart_port *port = &atmel_port->uart;
2501 atmel_init_property(atmel_port, pdev);
2515 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2522 if (!atmel_port->clk) {
2523 atmel_port->clk = clk_get(&mpdev->dev, "usart");
2524 if (IS_ERR(atmel_port->clk)) {
2525 ret = PTR_ERR(atmel_port->clk);
2526 atmel_port->clk = NULL;
2529 ret = clk_prepare_enable(atmel_port->clk);
2531 clk_put(atmel_port->clk);
2532 atmel_port->clk = NULL;
2535 port->uartclk = clk_get_rate(atmel_port->clk);
2536 clk_disable_unprepare(atmel_port->clk);
2545 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2548 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2550 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2570 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2579 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2587 atmel_port->tx_stopped = false;
2643 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2661 atmel_port->tx_stopped = false;
2713 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2726 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2727 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2728 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2729 atmel_port->cache.rtor = atmel_uart_readl(port,
2730 atmel_port->rtor);
2731 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2732 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2733 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2737 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2741 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2742 atmel_port->suspended = true;
2743 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2755 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2759 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2760 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2761 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2762 atmel_uart_writel(port, atmel_port->rtor,
2763 atmel_port->cache.rtor);
2764 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2766 if (atmel_port->fifo_size) {
2770 atmel_port->cache.fmr);
2772 atmel_port->cache.fimr);
2777 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2778 if (atmel_port->pending) {
2779 atmel_handle_receive(port, atmel_port->pending);
2780 atmel_handle_status(port, atmel_port->pending,
2781 atmel_port->pending_status);
2782 atmel_handle_transmit(port, atmel_port->pending);
2783 atmel_port->pending = 0;
2785 atmel_port->suspended = false;
2786 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2789 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2798 static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2801 atmel_port->fifo_size = 0;
2802 atmel_port->rts_low = 0;
2803 atmel_port->rts_high = 0;
2807 &atmel_port->fifo_size))
2810 if (!atmel_port->fifo_size)
2813 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2814 atmel_port->fifo_size = 0;
2827 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2828 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2829 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2830 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2833 atmel_port->fifo_size);
2835 atmel_port->rts_high);
2837 atmel_port->rts_low);
2842 struct atmel_uart_port *atmel_port;
2876 atmel_port = &atmel_ports[ret];
2877 atmel_port->backup_imr = 0;
2878 atmel_port->uart.line = ret;
2879 atmel_port->uart.has_sysrq = IS_ENABLED(CONFIG_SERIAL_ATMEL_CONSOLE);
2880 atmel_serial_probe_fifos(atmel_port, pdev);
2882 atomic_set(&atmel_port->tasklet_shutdown, 0);
2883 spin_lock_init(&atmel_port->lock_suspended);
2885 ret = atmel_init_port(atmel_port, pdev);
2889 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2890 if (IS_ERR(atmel_port->gpios)) {
2891 ret = PTR_ERR(atmel_port->gpios);
2895 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2902 atmel_port->rx_ring.buf = data;
2905 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2907 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2912 if (uart_console(&atmel_port->uart)
2918 clk_disable_unprepare(atmel_port->clk);
2923 platform_set_drvdata(pdev, atmel_port);
2929 clk_prepare_enable(atmel_port->clk);
2932 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2934 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2941 atmel_get_ip_name(&atmel_port->uart);
2947 clk_disable_unprepare(atmel_port->clk);
2952 kfree(atmel_port->rx_ring.buf);
2953 atmel_port->rx_ring.buf = NULL;
2955 if (!uart_console(&atmel_port->uart)) {
2956 clk_put(atmel_port->clk);
2957 atmel_port->clk = NULL;
2960 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2977 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2980 tasklet_kill(&atmel_port->tasklet_rx);
2981 tasklet_kill(&atmel_port->tasklet_tx);
2987 kfree(atmel_port->rx_ring.buf);
2993 clk_put(atmel_port->clk);
2994 atmel_port->clk = NULL;