Lines Matching defs:uap
280 static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,
283 return uap->reg_offset[reg];
286 static unsigned int pl011_read(const struct uart_amba_port *uap,
289 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
291 return (uap->port.iotype == UPIO_MEM32) ?
295 static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
298 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
300 if (uap->port.iotype == UPIO_MEM32)
311 static int pl011_fifo_to_tty(struct uart_amba_port *uap)
318 status = pl011_read(uap, REG_FR);
323 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
325 uap->port.icount.rx++;
330 uap->port.icount.brk++;
331 if (uart_handle_break(&uap->port))
334 uap->port.icount.parity++;
336 uap->port.icount.frame++;
338 uap->port.icount.overrun++;
340 ch &= uap->port.read_status_mask;
350 spin_unlock(&uap->port.lock);
351 sysrq = uart_handle_sysrq_char(&uap->port, ch & 255);
352 spin_lock(&uap->port.lock);
355 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
392 static void pl011_dma_probe(struct uart_amba_port *uap)
395 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
396 struct device *dev = uap->port.dev;
398 .dst_addr = uap->port.mapbase +
399 pl011_reg_to_offset(uap, REG_DR),
402 .dst_maxburst = uap->fifosize >> 1,
408 uap->dma_probed = true;
412 uap->dma_probed = false;
418 dev_info(uap->port.dev, "no DMA platform data\n");
429 dev_err(uap->port.dev, "no TX DMA channel!\n");
435 uap->dmatx.chan = chan;
437 dev_info(uap->port.dev, "DMA channel TX %s\n",
438 dma_chan_name(uap->dmatx.chan));
447 dev_err(uap->port.dev, "no RX DMA channel!\n");
454 .src_addr = uap->port.mapbase +
455 pl011_reg_to_offset(uap, REG_DR),
458 .src_maxburst = uap->fifosize >> 2,
472 dev_info(uap->port.dev,
478 uap->dmarx.chan = chan;
480 uap->dmarx.auto_poll_rate = false;
484 uap->dmarx.auto_poll_rate = false;
485 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
492 uap->dmarx.auto_poll_rate = true;
493 uap->dmarx.poll_rate = 100;
497 uap->dmarx.poll_timeout =
500 uap->dmarx.poll_timeout = 3000;
502 uap->dmarx.auto_poll_rate = of_property_read_bool(
504 if (uap->dmarx.auto_poll_rate) {
509 uap->dmarx.poll_rate = x;
511 uap->dmarx.poll_rate = 100;
514 uap->dmarx.poll_timeout = x;
516 uap->dmarx.poll_timeout = 3000;
519 dev_info(uap->port.dev, "DMA channel RX %s\n",
520 dma_chan_name(uap->dmarx.chan));
524 static void pl011_dma_remove(struct uart_amba_port *uap)
526 if (uap->dmatx.chan)
527 dma_release_channel(uap->dmatx.chan);
528 if (uap->dmarx.chan)
529 dma_release_channel(uap->dmarx.chan);
533 static int pl011_dma_tx_refill(struct uart_amba_port *uap);
534 static void pl011_start_tx_pio(struct uart_amba_port *uap);
542 struct uart_amba_port *uap = data;
543 struct pl011_dmatx_data *dmatx = &uap->dmatx;
547 spin_lock_irqsave(&uap->port.lock, flags);
548 if (uap->dmatx.queued)
552 dmacr = uap->dmacr;
553 uap->dmacr = dmacr & ~UART011_TXDMAE;
554 pl011_write(uap->dmacr, uap, REG_DMACR);
565 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
566 uart_circ_empty(&uap->port.state->xmit)) {
567 uap->dmatx.queued = false;
568 spin_unlock_irqrestore(&uap->port.lock, flags);
572 if (pl011_dma_tx_refill(uap) <= 0)
577 pl011_start_tx_pio(uap);
579 spin_unlock_irqrestore(&uap->port.lock, flags);
590 static int pl011_dma_tx_refill(struct uart_amba_port *uap)
592 struct pl011_dmatx_data *dmatx = &uap->dmatx;
596 struct circ_buf *xmit = &uap->port.state->xmit;
606 if (count < (uap->fifosize >> 1)) {
607 uap->dmatx.queued = false;
640 uap->dmatx.queued = false;
641 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
649 uap->dmatx.queued = false;
654 dev_dbg(uap->port.dev, "TX DMA busy\n");
660 desc->callback_param = uap;
668 uap->dmacr |= UART011_TXDMAE;
669 pl011_write(uap->dmacr, uap, REG_DMACR);
670 uap->dmatx.queued = true;
677 uap->port.icount.tx += count;
680 uart_write_wakeup(&uap->port);
693 static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
695 if (!uap->using_tx_dma)
703 if (uap->dmatx.queued) {
704 uap->dmacr |= UART011_TXDMAE;
705 pl011_write(uap->dmacr, uap, REG_DMACR);
706 uap->im &= ~UART011_TXIM;
707 pl011_write(uap->im, uap, REG_IMSC);
715 if (pl011_dma_tx_refill(uap) > 0) {
716 uap->im &= ~UART011_TXIM;
717 pl011_write(uap->im, uap, REG_IMSC);
727 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
729 if (uap->dmatx.queued) {
730 uap->dmacr &= ~UART011_TXDMAE;
731 pl011_write(uap->dmacr, uap, REG_DMACR);
743 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
747 if (!uap->using_tx_dma)
750 if (!uap->port.x_char) {
754 if (!uap->dmatx.queued) {
755 if (pl011_dma_tx_refill(uap) > 0) {
756 uap->im &= ~UART011_TXIM;
757 pl011_write(uap->im, uap, REG_IMSC);
760 } else if (!(uap->dmacr & UART011_TXDMAE)) {
761 uap->dmacr |= UART011_TXDMAE;
762 pl011_write(uap->dmacr, uap, REG_DMACR);
771 dmacr = uap->dmacr;
772 uap->dmacr &= ~UART011_TXDMAE;
773 pl011_write(uap->dmacr, uap, REG_DMACR);
775 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
784 pl011_write(uap->port.x_char, uap, REG_DR);
785 uap->port.icount.tx++;
786 uap->port.x_char = 0;
789 uap->dmacr = dmacr;
790 pl011_write(dmacr, uap, REG_DMACR);
800 __releases(&uap->port.lock)
801 __acquires(&uap->port.lock)
803 struct uart_amba_port *uap =
806 if (!uap->using_tx_dma)
809 dmaengine_terminate_async(uap->dmatx.chan);
811 if (uap->dmatx.queued) {
812 dma_unmap_single(uap->dmatx.chan->device->dev, uap->dmatx.dma,
813 uap->dmatx.len, DMA_TO_DEVICE);
814 uap->dmatx.queued = false;
815 uap->dmacr &= ~UART011_TXDMAE;
816 pl011_write(uap->dmacr, uap, REG_DMACR);
822 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
824 struct dma_chan *rxchan = uap->dmarx.chan;
825 struct pl011_dmarx_data *dmarx = &uap->dmarx;
833 dbuf = uap->dmarx.use_buf_b ?
834 &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a;
844 uap->dmarx.running = false;
851 desc->callback_param = uap;
855 uap->dmacr |= UART011_RXDMAE;
856 pl011_write(uap->dmacr, uap, REG_DMACR);
857 uap->dmarx.running = true;
859 uap->im &= ~UART011_RXIM;
860 pl011_write(uap->im, uap, REG_IMSC);
868 * with the port spinlock uap->port.lock held.
870 static void pl011_dma_rx_chars(struct uart_amba_port *uap,
874 struct tty_port *port = &uap->port.state->port;
876 &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a;
880 struct pl011_dmarx_data *dmarx = &uap->dmarx;
883 if (uap->dmarx.poll_rate) {
902 uap->port.icount.rx += dma_count;
904 dev_warn(uap->port.dev,
909 if (uap->dmarx.poll_rate)
919 UART011_FEIS, uap, REG_ICR);
932 fifotaken = pl011_fifo_to_tty(uap);
935 spin_unlock(&uap->port.lock);
936 dev_vdbg(uap->port.dev,
940 spin_lock(&uap->port.lock);
943 static void pl011_dma_rx_irq(struct uart_amba_port *uap)
945 struct pl011_dmarx_data *dmarx = &uap->dmarx;
959 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
963 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
966 uap->dmacr &= ~UART011_RXDMAE;
967 pl011_write(uap->dmacr, uap, REG_DMACR);
968 uap->dmarx.running = false;
979 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
983 if (pl011_dma_rx_trigger_dma(uap)) {
984 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
986 uap->im |= UART011_RXIM;
987 pl011_write(uap->im, uap, REG_IMSC);
993 struct uart_amba_port *uap = data;
994 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1010 spin_lock_irq(&uap->port.lock);
1021 uap->dmarx.running = false;
1023 ret = pl011_dma_rx_trigger_dma(uap);
1025 pl011_dma_rx_chars(uap, pending, lastbuf, false);
1026 spin_unlock_irq(&uap->port.lock);
1032 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
1034 uap->im |= UART011_RXIM;
1035 pl011_write(uap->im, uap, REG_IMSC);
1044 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1046 if (!uap->using_rx_dma)
1050 uap->dmacr &= ~UART011_RXDMAE;
1051 pl011_write(uap->dmacr, uap, REG_DMACR);
1061 struct uart_amba_port *uap = from_timer(uap, t, dmarx.timer);
1062 struct tty_port *port = &uap->port.state->port;
1063 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1064 struct dma_chan *rxchan = uap->dmarx.chan;
1072 dbuf = dmarx->use_buf_b ? &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a;
1090 > uap->dmarx.poll_timeout) {
1092 spin_lock_irqsave(&uap->port.lock, flags);
1093 pl011_dma_rx_stop(uap);
1094 uap->im |= UART011_RXIM;
1095 pl011_write(uap->im, uap, REG_IMSC);
1096 spin_unlock_irqrestore(&uap->port.lock, flags);
1098 uap->dmarx.running = false;
1100 del_timer(&uap->dmarx.timer);
1102 mod_timer(&uap->dmarx.timer,
1103 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1107 static void pl011_dma_startup(struct uart_amba_port *uap)
1111 if (!uap->dma_probed)
1112 pl011_dma_probe(uap);
1114 if (!uap->dmatx.chan)
1117 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
1118 if (!uap->dmatx.buf) {
1119 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
1120 uap->port.fifosize = uap->fifosize;
1124 uap->dmatx.len = PL011_DMA_BUFFER_SIZE;
1127 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
1128 uap->using_tx_dma = true;
1130 if (!uap->dmarx.chan)
1134 ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_a,
1137 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1142 ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_b,
1145 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1147 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a,
1152 uap->using_rx_dma = true;
1156 uap->dmacr |= UART011_DMAONERR;
1157 pl011_write(uap->dmacr, uap, REG_DMACR);
1164 if (uap->vendor->dma_threshold)
1166 uap, REG_ST_DMAWM);
1168 if (uap->using_rx_dma) {
1169 if (pl011_dma_rx_trigger_dma(uap))
1170 dev_dbg(uap->port.dev, "could not trigger initial "
1172 if (uap->dmarx.poll_rate) {
1173 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0);
1174 mod_timer(&uap->dmarx.timer,
1176 msecs_to_jiffies(uap->dmarx.poll_rate));
1177 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1178 uap->dmarx.last_jiffies = jiffies;
1183 static void pl011_dma_shutdown(struct uart_amba_port *uap)
1185 if (!(uap->using_tx_dma || uap->using_rx_dma))
1189 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
1192 spin_lock_irq(&uap->port.lock);
1193 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
1194 pl011_write(uap->dmacr, uap, REG_DMACR);
1195 spin_unlock_irq(&uap->port.lock);
1197 if (uap->using_tx_dma) {
1199 dmaengine_terminate_all(uap->dmatx.chan);
1200 if (uap->dmatx.queued) {
1201 dma_unmap_single(uap->dmatx.chan->device->dev,
1202 uap->dmatx.dma, uap->dmatx.len,
1204 uap->dmatx.queued = false;
1207 kfree(uap->dmatx.buf);
1208 uap->using_tx_dma = false;
1211 if (uap->using_rx_dma) {
1212 dmaengine_terminate_all(uap->dmarx.chan);
1214 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a, DMA_FROM_DEVICE);
1215 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_b, DMA_FROM_DEVICE);
1216 if (uap->dmarx.poll_rate)
1217 del_timer_sync(&uap->dmarx.timer);
1218 uap->using_rx_dma = false;
1222 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1224 return uap->using_rx_dma;
1227 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1229 return uap->using_rx_dma && uap->dmarx.running;
1234 static inline void pl011_dma_remove(struct uart_amba_port *uap)
1238 static inline void pl011_dma_startup(struct uart_amba_port *uap)
1242 static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1246 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1251 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1255 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1260 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1264 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1268 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1273 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1278 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1288 struct uart_amba_port *uap =
1291 uap->im &= ~UART011_TXIM;
1292 pl011_write(uap->im, uap, REG_IMSC);
1293 pl011_dma_tx_stop(uap);
1296 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
1299 static void pl011_start_tx_pio(struct uart_amba_port *uap)
1301 if (pl011_tx_chars(uap, false)) {
1302 uap->im |= UART011_TXIM;
1303 pl011_write(uap->im, uap, REG_IMSC);
1309 struct uart_amba_port *uap =
1312 if (!pl011_dma_tx_start(uap))
1313 pl011_start_tx_pio(uap);
1318 struct uart_amba_port *uap =
1321 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1323 pl011_write(uap->im, uap, REG_IMSC);
1325 pl011_dma_rx_stop(uap);
1339 struct uart_amba_port *uap =
1342 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1343 pl011_write(uap->im, uap, REG_IMSC);
1346 static void pl011_rx_chars(struct uart_amba_port *uap)
1347 __releases(&uap->port.lock)
1348 __acquires(&uap->port.lock)
1350 pl011_fifo_to_tty(uap);
1352 spin_unlock(&uap->port.lock);
1353 tty_flip_buffer_push(&uap->port.state->port);
1358 if (pl011_dma_rx_available(uap)) {
1359 if (pl011_dma_rx_trigger_dma(uap)) {
1360 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1362 uap->im |= UART011_RXIM;
1363 pl011_write(uap->im, uap, REG_IMSC);
1367 if (uap->dmarx.poll_rate) {
1368 uap->dmarx.last_jiffies = jiffies;
1369 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1370 mod_timer(&uap->dmarx.timer,
1372 msecs_to_jiffies(uap->dmarx.poll_rate));
1377 spin_lock(&uap->port.lock);
1380 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
1384 pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1387 pl011_write(c, uap, REG_DR);
1388 uap->port.icount.tx++;
1394 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
1396 struct circ_buf *xmit = &uap->port.state->xmit;
1397 int count = uap->fifosize >> 1;
1399 if (uap->port.x_char) {
1400 if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
1402 uap->port.x_char = 0;
1405 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1406 pl011_stop_tx(&uap->port);
1411 if (pl011_dma_tx_irq(uap))
1418 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
1425 uart_write_wakeup(&uap->port);
1428 pl011_stop_tx(&uap->port);
1434 static void pl011_modem_status(struct uart_amba_port *uap)
1438 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1440 delta = status ^ uap->old_status;
1441 uap->old_status = status;
1447 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1449 if (delta & uap->vendor->fr_dsr)
1450 uap->port.icount.dsr++;
1452 if (delta & uap->vendor->fr_cts)
1453 uart_handle_cts_change(&uap->port,
1454 status & uap->vendor->fr_cts);
1456 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1459 static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1461 if (!uap->vendor->cts_event_workaround)
1465 pl011_write(0x00, uap, REG_ICR);
1472 pl011_read(uap, REG_ICR);
1473 pl011_read(uap, REG_ICR);
1478 struct uart_amba_port *uap = dev_id;
1483 spin_lock_irqsave(&uap->port.lock, flags);
1484 status = pl011_read(uap, REG_RIS) & uap->im;
1487 check_apply_cts_event_workaround(uap);
1491 uap, REG_ICR);
1494 if (pl011_dma_rx_running(uap))
1495 pl011_dma_rx_irq(uap);
1497 pl011_rx_chars(uap);
1501 pl011_modem_status(uap);
1503 pl011_tx_chars(uap, true);
1508 status = pl011_read(uap, REG_RIS) & uap->im;
1513 spin_unlock_irqrestore(&uap->port.lock, flags);
1520 struct uart_amba_port *uap =
1524 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr;
1526 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ?
1532 struct uart_amba_port *uap =
1535 unsigned int status = pl011_read(uap, REG_FR);
1542 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR);
1543 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS);
1544 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG);
1551 struct uart_amba_port *uap =
1555 cr = pl011_read(uap, REG_CR);
1575 pl011_write(cr, uap, REG_CR);
1580 struct uart_amba_port *uap =
1585 spin_lock_irqsave(&uap->port.lock, flags);
1586 lcr_h = pl011_read(uap, REG_LCRH_TX);
1591 pl011_write(lcr_h, uap, REG_LCRH_TX);
1592 spin_unlock_irqrestore(&uap->port.lock, flags);
1599 struct uart_amba_port *uap =
1602 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
1616 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
1622 struct uart_amba_port *uap =
1632 status = pl011_read(uap, REG_FR);
1636 return pl011_read(uap, REG_DR);
1642 struct uart_amba_port *uap =
1645 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1648 pl011_write(ch, uap, REG_DR);
1655 struct uart_amba_port *uap =
1665 retval = clk_prepare_enable(uap->clk);
1669 uap->port.uartclk = clk_get_rate(uap->clk);
1674 uap, REG_ICR);
1680 uap->im = pl011_read(uap, REG_IMSC);
1681 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);
1683 if (dev_get_platdata(uap->port.dev)) {
1686 plat = dev_get_platdata(uap->port.dev);
1693 static bool pl011_split_lcrh(const struct uart_amba_port *uap)
1695 return pl011_reg_to_offset(uap, REG_LCRH_RX) !=
1696 pl011_reg_to_offset(uap, REG_LCRH_TX);
1699 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
1701 pl011_write(lcr_h, uap, REG_LCRH_RX);
1702 if (pl011_split_lcrh(uap)) {
1709 pl011_write(0xff, uap, REG_MIS);
1710 pl011_write(lcr_h, uap, REG_LCRH_TX);
1714 static int pl011_allocate_irq(struct uart_amba_port *uap)
1716 pl011_write(uap->im, uap, REG_IMSC);
1718 return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap);
1726 static void pl011_enable_interrupts(struct uart_amba_port *uap)
1731 spin_lock_irqsave(&uap->port.lock, flags);
1734 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
1742 for (i = 0; i < uap->fifosize * 2; ++i) {
1743 if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE)
1746 pl011_read(uap, REG_DR);
1749 uap->im = UART011_RTIM;
1750 if (!pl011_dma_rx_running(uap))
1751 uap->im |= UART011_RXIM;
1752 pl011_write(uap->im, uap, REG_IMSC);
1753 spin_unlock_irqrestore(&uap->port.lock, flags);
1758 struct uart_amba_port *uap = container_of(port, struct uart_amba_port, port);
1761 spin_lock_irqsave(&uap->port.lock, flags);
1763 uap->im = UART011_RTIM;
1764 if (!pl011_dma_rx_running(uap))
1765 uap->im |= UART011_RXIM;
1767 pl011_write(uap->im, uap, REG_IMSC);
1769 spin_unlock_irqrestore(&uap->port.lock, flags);
1774 struct uart_amba_port *uap =
1783 retval = pl011_allocate_irq(uap);
1787 pl011_write(uap->vendor->ifls, uap, REG_IFLS);
1789 spin_lock_irq(&uap->port.lock);
1792 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1794 pl011_write(cr, uap, REG_CR);
1796 spin_unlock_irq(&uap->port.lock);
1801 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1804 pl011_dma_startup(uap);
1806 pl011_enable_interrupts(uap);
1811 clk_disable_unprepare(uap->clk);
1817 struct uart_amba_port *uap =
1825 retval = pl011_allocate_irq(uap);
1830 uap->old_status = 0;
1832 pl011_enable_interrupts(uap);
1837 static void pl011_shutdown_channel(struct uart_amba_port *uap,
1842 val = pl011_read(uap, lcrh);
1844 pl011_write(val, uap, lcrh);
1852 static void pl011_disable_uart(struct uart_amba_port *uap)
1856 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1857 spin_lock_irq(&uap->port.lock);
1858 cr = pl011_read(uap, REG_CR);
1859 uap->old_cr = cr;
1862 pl011_write(cr, uap, REG_CR);
1863 spin_unlock_irq(&uap->port.lock);
1868 pl011_shutdown_channel(uap, REG_LCRH_RX);
1869 if (pl011_split_lcrh(uap))
1870 pl011_shutdown_channel(uap, REG_LCRH_TX);
1873 static void pl011_disable_interrupts(struct uart_amba_port *uap)
1875 spin_lock_irq(&uap->port.lock);
1878 uap->im = 0;
1879 pl011_write(uap->im, uap, REG_IMSC);
1880 pl011_write(0xffff, uap, REG_ICR);
1882 spin_unlock_irq(&uap->port.lock);
1887 struct uart_amba_port *uap =
1890 pl011_disable_interrupts(uap);
1892 pl011_dma_shutdown(uap);
1894 free_irq(uap->port.irq, uap);
1896 pl011_disable_uart(uap);
1901 clk_disable_unprepare(uap->clk);
1905 if (dev_get_platdata(uap->port.dev)) {
1908 plat = dev_get_platdata(uap->port.dev);
1913 if (uap->port.ops->flush_buffer)
1914 uap->port.ops->flush_buffer(port);
1919 struct uart_amba_port *uap =
1922 pl011_disable_interrupts(uap);
1924 free_irq(uap->port.irq, uap);
1926 if (uap->port.ops->flush_buffer)
1927 uap->port.ops->flush_buffer(port);
1966 struct uart_amba_port *uap =
1972 if (uap->vendor->oversampling)
1986 if (uap->dmarx.auto_poll_rate)
1987 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
2018 if (uap->fifosize > 1)
2034 old_cr = pl011_read(uap, REG_CR);
2035 pl011_write(0, uap, REG_CR);
2048 if (uap->vendor->oversampling) {
2061 if (uap->vendor->oversampling) {
2068 pl011_write(quot & 0x3f, uap, REG_FBRD);
2069 pl011_write(quot >> 6, uap, REG_IBRD);
2077 pl011_write_lcr_h(uap, lcr_h);
2078 pl011_write(old_cr, uap, REG_CR);
2087 struct uart_amba_port *uap =
2091 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);
2099 uart_update_timeout(port, CS8, uap->fixed_baud);
2106 struct uart_amba_port *uap =
2108 return uap->port.type == PORT_AMBA ? uap->type : NULL;
2197 struct uart_amba_port *uap =
2200 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2202 pl011_write(ch, uap, REG_DR);
2208 struct uart_amba_port *uap = amba_ports[co->index];
2213 clk_enable(uap->clk);
2216 if (uap->port.sysrq)
2219 locked = spin_trylock(&uap->port.lock);
2221 spin_lock(&uap->port.lock);
2226 if (!uap->vendor->always_enabled) {
2227 old_cr = pl011_read(uap, REG_CR);
2230 pl011_write(new_cr, uap, REG_CR);
2233 uart_console_write(&uap->port, s, count, pl011_console_putchar);
2240 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)
2241 & uap->vendor->fr_busy)
2243 if (!uap->vendor->always_enabled)
2244 pl011_write(old_cr, uap, REG_CR);
2247 spin_unlock(&uap->port.lock);
2250 clk_disable(uap->clk);
2253 static void pl011_console_get_options(struct uart_amba_port *uap, int *baud,
2256 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) {
2259 lcr_h = pl011_read(uap, REG_LCRH_TX);
2274 ibrd = pl011_read(uap, REG_IBRD);
2275 fbrd = pl011_read(uap, REG_FBRD);
2277 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
2279 if (uap->vendor->oversampling) {
2280 if (pl011_read(uap, REG_CR)
2289 struct uart_amba_port *uap;
2303 uap = amba_ports[co->index];
2304 if (!uap)
2308 pinctrl_pm_select_default_state(uap->port.dev);
2310 ret = clk_prepare(uap->clk);
2314 if (dev_get_platdata(uap->port.dev)) {
2317 plat = dev_get_platdata(uap->port.dev);
2322 uap->port.uartclk = clk_get_rate(uap->clk);
2324 if (uap->vendor->fixed_options) {
2325 baud = uap->fixed_baud;
2331 pl011_console_get_options(uap, &baud, &parity, &bits);
2334 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2572 static void pl011_unregister_port(struct uart_amba_port *uap)
2578 if (amba_ports[i] == uap)
2583 pl011_dma_remove(uap);
2599 static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
2610 uap->old_cr = 0;
2611 uap->port.dev = dev;
2612 uap->port.mapbase = mmiobase->start;
2613 uap->port.membase = base;
2614 uap->port.fifosize = uap->fifosize;
2615 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE);
2616 uap->port.flags = UPF_BOOT_AUTOCONF;
2617 uap->port.line = index;
2619 amba_ports[index] = uap;
2624 static int pl011_register_port(struct uart_amba_port *uap)
2629 pl011_write(0, uap, REG_IMSC);
2630 pl011_write(0xffff, uap, REG_ICR);
2635 dev_err(uap->port.dev,
2638 if (amba_ports[i] == uap)
2644 ret = uart_add_one_port(&amba_reg, &uap->port);
2646 pl011_unregister_port(uap);
2653 struct uart_amba_port *uap;
2661 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2663 if (!uap)
2666 uap->clk = devm_clk_get(&dev->dev, NULL);
2667 if (IS_ERR(uap->clk))
2668 return PTR_ERR(uap->clk);
2670 uap->reg_offset = vendor->reg_offset;
2671 uap->vendor = vendor;
2672 uap->fifosize = vendor->get_fifosize(dev);
2673 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2674 uap->port.irq = dev->irq[0];
2675 uap->port.ops = &amba_pl011_pops;
2677 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2679 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
2683 amba_set_drvdata(dev, uap);
2685 return pl011_register_port(uap);
2690 struct uart_amba_port *uap = amba_get_drvdata(dev);
2692 uart_remove_one_port(&amba_reg, &uap->port);
2693 pl011_unregister_port(uap);
2699 struct uart_amba_port *uap = dev_get_drvdata(dev);
2701 if (!uap)
2704 return uart_suspend_port(&amba_reg, &uap->port);
2709 struct uart_amba_port *uap = dev_get_drvdata(dev);
2711 if (!uap)
2714 return uart_resume_port(&amba_reg, &uap->port);
2722 struct uart_amba_port *uap;
2745 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
2747 if (!uap)
2753 uap->port.irq = ret;
2758 uap->vendor = &vendor_qdt_qdf2400_e44;
2761 uap->vendor = &vendor_sbsa;
2763 uap->reg_offset = uap->vendor->reg_offset;
2764 uap->fifosize = 32;
2765 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2766 uap->port.ops = &sbsa_uart_pops;
2767 uap->fixed_baud = baudrate;
2769 snprintf(uap->type, sizeof(uap->type), "SBSA");
2773 ret = pl011_setup_port(&pdev->dev, uap, r, portnr);
2777 platform_set_drvdata(pdev, uap);
2779 return pl011_register_port(uap);
2784 struct uart_amba_port *uap = platform_get_drvdata(pdev);
2786 uart_remove_one_port(&amba_reg, &uap->port);
2787 pl011_unregister_port(uap);