Lines Matching refs:port
88 setup_port(struct serial_private *priv, struct uart_8250_port *port,
100 port->port.iotype = UPIO_MEM;
101 port->port.iobase = 0;
102 port->port.mapbase = pci_resource_start(dev, bar) + offset;
103 port->port.membase = pcim_iomap_table(dev)[bar] + offset;
104 port->port.regshift = regshift;
106 port->port.iotype = UPIO_PORT;
107 port->port.iobase = pci_resource_start(dev, bar) + offset;
108 port->port.mapbase = 0;
109 port->port.membase = NULL;
110 port->port.regshift = 0;
120 struct uart_8250_port *port, int idx)
138 return setup_port(priv, port, bar, offset, board->reg_shift);
147 struct uart_8250_port *port, int idx)
159 return setup_port(priv, port, bar, offset, board->reg_shift);
196 * HP's Diva chip puts the 4th/5th serial port further out, and
202 struct uart_8250_port *port, int idx)
224 return setup_port(priv, port, bar, offset, board->reg_shift);
371 struct uart_8250_port *port, int idx)
386 return setup_port(priv, port, bar, offset, board->reg_shift);
526 struct uart_8250_port *port, int idx)
535 return setup_port(priv, port, bar, offset, 0);
580 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
619 struct uart_8250_port *port, int idx)
644 return setup_port(priv, port, bar, offset, board->reg_shift);
653 struct uart_8250_port *port, int idx)
669 return setup_port(priv, port, bar, offset, board->reg_shift);
754 struct uart_8250_port *port, int idx)
776 return setup_port(priv, port, bar, offset, board->reg_shift);
781 struct uart_8250_port *port, int idx)
792 return setup_port(priv, port, bar, 0, board->reg_shift);
794 return pci_default_setup(priv, board, port, idx);
828 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
870 * These chips are available with optionally one parallel port and up to
955 /* read the I/O port from the device */
1101 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device);
1105 static int pci_quatech_rqopr(struct uart_8250_port *port)
1107 unsigned long base = port->port.iobase;
1117 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1119 unsigned long base = port->port.iobase;
1129 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1131 unsigned long base = port->port.iobase;
1145 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1147 unsigned long base = port->port.iobase;
1159 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1161 unsigned long base = port->port.iobase;
1177 static int pci_quatech_test(struct uart_8250_port *port)
1181 qopr = pci_quatech_rqopr(port);
1182 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1183 reg = pci_quatech_rqopr(port) & 0xC0;
1186 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1187 reg = pci_quatech_rqopr(port) & 0xC0;
1190 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1191 reg = pci_quatech_rqopr(port) & 0xC0;
1194 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1195 reg = pci_quatech_rqopr(port) & 0xC0;
1199 pci_quatech_wqopr(port, qopr);
1203 static int pci_quatech_clock(struct uart_8250_port *port)
1208 if (pci_quatech_test(port) < 0)
1211 qopr = pci_quatech_rqopr(port);
1213 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1214 reg = pci_quatech_rqopr(port);
1219 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1220 reg = pci_quatech_rqopr(port);
1243 pci_quatech_wqopr(port, qopr);
1247 static int pci_quatech_rs422(struct uart_8250_port *port)
1252 if (!pci_quatech_has_qmcr(port))
1254 qmcr = pci_quatech_rqmcr(port);
1255 pci_quatech_wqmcr(port, 0xFF);
1256 if (pci_quatech_rqmcr(port))
1258 pci_quatech_wqmcr(port, qmcr);
1280 struct uart_8250_port *port, int idx)
1283 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1285 port->port.uartclk = pci_quatech_clock(port);
1287 if (pci_quatech_rs422(port))
1289 return pci_default_setup(priv, board, port, idx);
1298 struct uart_8250_port *port, int idx)
1314 return setup_port(priv, port, bar, offset, board->reg_shift);
1317 pericom_do_set_divisor(struct uart_port *port, unsigned int baud,
1324 unsigned int maxrate = port->uartclk / scr;
1340 lcr = serial_port_in(port, UART_LCR);
1341 serial_port_out(port, UART_LCR, lcr | 0x80);
1342 serial_port_out(port, UART_DLL, divisor & 0xff);
1343 serial_port_out(port, UART_DLM, divisor >> 8 & 0xff);
1344 serial_port_out(port, 2, 16 - scr);
1345 serial_port_out(port, UART_LCR, lcr);
1352 struct uart_8250_port *port, int idx)
1369 port->port.set_divisor = pericom_do_set_divisor;
1371 return setup_port(priv, port, bar, offset, board->reg_shift);
1376 struct uart_8250_port *port, int idx)
1395 port->port.set_divisor = pericom_do_set_divisor;
1397 return setup_port(priv, port, bar, offset, board->reg_shift);
1403 struct uart_8250_port *port, int idx)
1407 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1408 port->port.iotype = UPIO_MEM32;
1409 port->port.type = PORT_XSCALE;
1410 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1411 port->port.regshift = 2;
1419 struct uart_8250_port *port, int idx)
1421 return setup_port(priv, port, 2, idx * 8, 0);
1427 struct uart_8250_port *port, int idx)
1429 int ret = pci_default_setup(priv, board, port, idx);
1431 port->port.type = PORT_BRCM_TRUMANAGE;
1432 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1442 static int pci_fintek_rs485_config(struct uart_port *port,
1445 struct pci_dev *pci_dev = to_pci_dev(port->dev);
1447 u8 *index = (u8 *) port->private_data;
1452 rs485 = &port->rs485;
1482 if (rs485 != &port->rs485)
1483 port->rs485 = *rs485;
1490 struct uart_8250_port *port, int idx)
1504 port->port.iotype = UPIO_PORT;
1505 port->port.iobase = iobase;
1506 port->port.rs485_config = pci_fintek_rs485_config;
1514 port->port.private_data = data;
1556 /* Enable UART I/O port */
1573 /* First init without port data
1596 struct uart_8250_port *port, int idx)
1608 port->port.private_data = data;
1609 port->port.iotype = UPIO_MEM;
1610 port->port.flags |= UPF_IOREMAP;
1611 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx;
1612 port->port.serial_out = f815xxa_mem_serial_out;
1647 /* Enable UART I/O port */
1656 struct uart_8250_port *port, int idx)
1658 port->port.quirks |= UPQ_NO_TXEN_TEST;
1664 return pci_default_setup(priv, board, port, idx);
1685 * port registers could return 0 momentarily. Functions like
1703 struct uart_8250_port *port, int idx)
1705 port->port.flags |= UPF_BUG_THRE;
1706 port->port.serial_in = kt_serial_in;
1707 port->port.handle_break = kt_handle_break;
1708 return skip_tx_en_setup(priv, board, port, idx);
1723 struct uart_8250_port *port, int idx)
1725 port->port.flags |= UPF_FIXED_TYPE;
1726 port->port.type = PORT_16550A;
1727 return pci_default_setup(priv, board, port, idx);
1733 struct uart_8250_port *port, int idx)
1735 port->port.flags |= UPF_FIXED_TYPE;
1736 port->port.type = PORT_16550A;
1737 return pci_default_setup(priv, board, port, idx);
1743 struct uart_8250_port *port, int idx)
1745 port->port.flags |= UPF_FIXED_TYPE;
1746 port->port.type = PORT_16850;
1747 return pci_default_setup(priv, board, port, idx);
1786 struct uart_8250_port *port, int idx)
1791 port->port.flags |= UPF_FIXED_TYPE;
1792 port->port.type = PORT_SUNIX;
1804 return setup_port(priv, port, bar, offset, 0);
1810 struct uart_8250_port *port, int idx)
1820 return setup_port(priv, port, bar, offset, 0);
1932 * Master list of serial port init/setup/exit quirks.
1933 * This does not describe the general nature of the port.
2192 * Pericom (Only 7954 - It have a offset jump for port 4)
2790 * offsetinhex = offset for each sequential port (in hex)
3463 * EKF addition for i960 Boards form EKF with serial port.
3854 * If there is 1 or 0 iomem regions, and exactly one port,
3946 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3947 uart.port.uartclk = board->base_baud * 16;
3950 uart.port.irq = 0;
3955 uart.port.flags &= ~UPF_SHARE_IRQ;
3967 uart.port.irq = pci_irq_vector(dev, 0);
3970 uart.port.dev = &dev->dev;
3976 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3977 uart.port.iobase, uart.port.irq, uart.port.iotype);
3982 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3983 uart.port.iobase, uart.port.irq,
3984 uart.port.iotype, priv->line[i]);
4612 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4933 * RAStel 2 port modem, gerg@moreton.com.au
4940 * EKF addition for i960 Boards form EKF with serial port