Lines Matching defs:uart
491 dev_warn(&pdev->dev, "Can't get uart clock\n");
523 struct uart_8250_port uart = {};
538 uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
540 if (!uart.port.membase)
550 err = mtk8250_probe_of(pdev, &uart.port, data);
556 spin_lock_init(&uart.port.lock);
557 uart.port.mapbase = regs->start;
558 uart.port.irq = irq;
559 uart.port.pm = mtk8250_do_pm;
560 uart.port.type = PORT_16550;
561 uart.port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
562 uart.port.dev = &pdev->dev;
563 uart.port.iotype = UPIO_MEM32;
564 uart.port.regshift = 2;
565 uart.port.private_data = data;
566 uart.port.shutdown = mtk8250_shutdown;
567 uart.port.startup = mtk8250_startup;
568 uart.port.set_termios = mtk8250_set_termios;
569 uart.port.uartclk = clk_get_rate(data->uart_clk);
572 uart.dma = data->dma;
576 writel(0x0, uart.port.membase +
577 (MTK_UART_RATE_FIX << uart.port.regshift));
586 data->line = serial8250_register_8250_port(&uart);
664 { .compatible = "mediatek,mt6577-uart" },
671 .name = "mt6577-uart",
693 OF_EARLYCON_DECLARE(mtk8250, "mediatek,mt6577-uart", early_mtk8250_setup);