Lines Matching refs:dma
10 #include <linux/dma-mapping.h>
17 struct uart_8250_dma *dma = p->dma;
22 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
27 dma->tx_running = 0;
29 xmit->tail += dma->tx_size;
31 p->port.icount.tx += dma->tx_size;
46 struct uart_8250_dma *dma = p->dma;
57 dma_status = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
61 count = dma->rx_size - state.residue;
63 tty_insert_flip_string(tty_port, dma->rx_buf, count);
65 dma->rx_running = 0;
73 struct uart_8250_dma *dma = p->dma;
77 if (dma->rx_running)
84 struct uart_8250_dma *dma = p->dma;
90 if (dma->tx_running) {
92 dmaengine_pause(dma->txchan);
94 dmaengine_resume(dma->txchan);
107 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
109 desc = dmaengine_prep_slave_single(dma->txchan,
110 dma->tx_addr + xmit->tail,
111 dma->tx_size, DMA_MEM_TO_DEV,
118 dma->tx_running = 1;
122 dma->tx_cookie = dmaengine_submit(desc);
124 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
127 dma_async_issue_pending(dma->txchan);
128 if (dma->tx_err) {
129 dma->tx_err = 0;
134 dma->tx_err = 1;
140 struct uart_8250_dma *dma = p->dma;
143 if (dma->rx_running)
146 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
147 dma->rx_size, DMA_DEV_TO_MEM,
152 dma->rx_running = 1;
156 dma->rx_cookie = dmaengine_submit(desc);
158 dma_async_issue_pending(dma->rxchan);
165 struct uart_8250_dma *dma = p->dma;
167 if (dma->rx_running) {
168 dmaengine_pause(dma->rxchan);
170 dmaengine_terminate_async(dma->rxchan);
177 struct uart_8250_dma *dma = p->dma;
178 phys_addr_t rx_dma_addr = dma->rx_dma_addr ?
179 dma->rx_dma_addr : p->port.mapbase;
180 phys_addr_t tx_dma_addr = dma->tx_dma_addr ?
181 dma->tx_dma_addr : p->port.mapbase;
187 dma->rxconf.direction = DMA_DEV_TO_MEM;
188 dma->rxconf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
189 dma->rxconf.src_addr = rx_dma_addr + UART_RX;
191 dma->txconf.direction = DMA_MEM_TO_DEV;
192 dma->txconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
193 dma->txconf.dst_addr = tx_dma_addr + UART_TX;
199 dma->rxchan = dma_request_slave_channel_compat(mask,
200 dma->fn, dma->rx_param,
202 if (!dma->rxchan)
205 /* 8250 rx dma requires dmaengine driver to support pause/terminate */
206 ret = dma_get_slave_caps(dma->rxchan, &caps);
215 dmaengine_slave_config(dma->rxchan, &dma->rxconf);
218 dma->txchan = dma_request_slave_channel_compat(mask,
219 dma->fn, dma->tx_param,
221 if (!dma->txchan) {
226 /* 8250 tx dma requires dmaengine driver to support terminate */
227 ret = dma_get_slave_caps(dma->txchan, &caps);
235 dmaengine_slave_config(dma->txchan, &dma->txconf);
238 if (!dma->rx_size)
239 dma->rx_size = PAGE_SIZE;
241 dma->rx_buf = dma_alloc_coherent(dma->rxchan->device->dev, dma->rx_size,
242 &dma->rx_addr, GFP_KERNEL);
243 if (!dma->rx_buf) {
249 dma->tx_addr = dma_map_single(dma->txchan->device->dev,
253 if (dma_mapping_error(dma->txchan->device->dev, dma->tx_addr)) {
254 dma_free_coherent(dma->rxchan->device->dev, dma->rx_size,
255 dma->rx_buf, dma->rx_addr);
260 dev_dbg_ratelimited(p->port.dev, "got both dma channels\n");
264 dma_release_channel(dma->txchan);
266 dma_release_channel(dma->rxchan);
273 struct uart_8250_dma *dma = p->dma;
275 if (!dma)
279 dmaengine_terminate_sync(dma->rxchan);
280 dma_free_coherent(dma->rxchan->device->dev, dma->rx_size, dma->rx_buf,
281 dma->rx_addr);
282 dma_release_channel(dma->rxchan);
283 dma->rxchan = NULL;
286 dmaengine_terminate_sync(dma->txchan);
287 dma_unmap_single(dma->txchan->device->dev, dma->tx_addr,
289 dma_release_channel(dma->txchan);
290 dma->txchan = NULL;
291 dma->tx_running = 0;
293 dev_dbg_ratelimited(p->port.dev, "dma channels released\n");