Lines Matching refs:TxControl
360 Byte_t TxControl[4];
384 (ChP)->TxControl[3] &= ~SETBREAK; \
385 out32((ChP)->IndexAddr,(ChP)->TxControl); \
396 (ChP)->TxControl[3] &= ~SET_DTR; \
397 out32((ChP)->IndexAddr,(ChP)->TxControl); \
409 (ChP)->TxControl[3] &= ~SET_RTS; \
410 out32((ChP)->IndexAddr,(ChP)->TxControl); \
483 (ChP)->TxControl[2] &= ~CTSFC_EN; \
484 out32((ChP)->IndexAddr,(ChP)->TxControl); \
509 (ChP)->TxControl[2] &= ~PARITY_EN; \
510 out32((ChP)->IndexAddr,(ChP)->TxControl); \
521 (ChP)->TxControl[2] &= ~RTSTOG_EN; \
522 out32((ChP)->IndexAddr,(ChP)->TxControl); \
561 (ChP)->TxControl[3] &= ~TX_ENABLE; \
562 out32((ChP)->IndexAddr,(ChP)->TxControl); \
598 (ChP)->TxControl[2] |= CTSFC_EN; \
599 out32((ChP)->IndexAddr,(ChP)->TxControl); \
627 (ChP)->TxControl[2] |= PARITY_EN; \
628 out32((ChP)->IndexAddr,(ChP)->TxControl); \
643 (ChP)->TxControl[2] |= RTSTOG_EN; \
644 (ChP)->TxControl[3] &= ~SET_RTS; \
645 out32((ChP)->IndexAddr,(ChP)->TxControl); \
702 (ChP)->TxControl[3] |= TX_ENABLE; \
703 out32((ChP)->IndexAddr,(ChP)->TxControl); \
921 (ChP)->TxControl[3] |= SETBREAK; \
922 out32((ChP)->IndexAddr,(ChP)->TxControl); \
947 (ChP)->TxControl[2] &= ~DATA8BIT; \
948 out32((ChP)->IndexAddr,(ChP)->TxControl); \
959 (ChP)->TxControl[2] |= DATA8BIT; \
960 out32((ChP)->IndexAddr,(ChP)->TxControl); \
971 (ChP)->TxControl[3] |= SET_DTR; \
972 out32((ChP)->IndexAddr,(ChP)->TxControl); \
988 (ChP)->TxControl[2] |= EVEN_PAR; \
989 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1005 (ChP)->TxControl[2] &= ~EVEN_PAR; \
1006 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1018 (ChP)->TxControl[3] |= SET_RTS; \
1019 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1056 (ChP)->TxControl[2] &= ~STOP2; \
1057 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1068 (ChP)->TxControl[2] |= STOP2; \
1069 out32((ChP)->IndexAddr,(ChP)->TxControl); \