Lines Matching refs:sOutW
1870 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2610 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2667 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2669 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2798 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2799 sOutW(ChP->IndexData, 0);
2805 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2806 sOutW(ChP->IndexData, 0);
2807 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2808 sOutW(ChP->IndexData, 0);
2810 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2813 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2884 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2885 sOutW(ChP->IndexData, 0);
2886 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2887 sOutW(ChP->IndexData, 0);
2926 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2927 sOutW(ChP->IndexData, 0);
2954 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */