Lines Matching refs:ChP
222 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
224 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
225 static void sFlushRxFIFO(CHANNEL_T * ChP);
226 static void sFlushTxFIFO(CHANNEL_T * ChP);
227 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
228 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
231 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
1105 static int sGetChanRI(CHANNEL_T * ChP)
1107 CONTROLLER_t *CtlP = ChP->CtlP;
1108 int ChanNum = ChP->ChanNum;
1114 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
2679 Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2681 CHANNEL_T *ChP; Ptr to channel structure
2691 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2706 ChP->CtlP = CtlP;
2707 ChP->ChanID = CtlP->AiopID[AiopNum];
2708 ChP->AiopNum = AiopNum;
2709 ChP->ChanNum = ChanNum;
2713 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2714 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2715 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2716 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2717 ChP->IndexData = AiopIO + _INDX_DATA;
2720 ChIOOff = AiopIO + ChP->ChanNum * 2;
2721 ChP->TxRxData = ChIOOff + _TD0;
2722 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2723 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2724 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2732 out32(ChP->IndexAddr, R);
2735 ChR = ChP->R;
2751 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2752 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2753 ChP->BaudDiv[2] = (Byte_t) brd9600;
2754 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2755 out32(ChP->IndexAddr, ChP->BaudDiv);
2757 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2758 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2759 ChP->TxControl[2] = 0;
2760 ChP->TxControl[3] = 0;
2761 out32(ChP->IndexAddr, ChP->TxControl);
2763 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2764 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2765 ChP->RxControl[2] = 0;
2766 ChP->RxControl[3] = 0;
2767 out32(ChP->IndexAddr, ChP->RxControl);
2769 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2770 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2771 ChP->TxEnables[2] = 0;
2772 ChP->TxEnables[3] = 0;
2773 out32(ChP->IndexAddr, ChP->TxEnables);
2775 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2776 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2777 ChP->TxCompare[2] = 0;
2778 ChP->TxCompare[3] = 0;
2779 out32(ChP->IndexAddr, ChP->TxCompare);
2781 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2782 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2783 ChP->TxReplace1[2] = 0;
2784 ChP->TxReplace1[3] = 0;
2785 out32(ChP->IndexAddr, ChP->TxReplace1);
2787 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2788 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2789 ChP->TxReplace2[2] = 0;
2790 ChP->TxReplace2[3] = 0;
2791 out32(ChP->IndexAddr, ChP->TxReplace2);
2793 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2794 ChP->TxFIFO = ChOff + _TX_FIFO;
2796 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2797 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2798 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2799 sOutW(ChP->IndexData, 0);
2800 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2801 ChP->RxFIFO = ChOff + _RX_FIFO;
2803 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2804 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2805 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2806 sOutW(ChP->IndexData, 0);
2807 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2808 sOutW(ChP->IndexData, 0);
2809 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2810 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2811 sOutB(ChP->IndexData, 0);
2812 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2813 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2814 sOutB(ChP->IndexData, 0);
2815 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2816 sEnRxProcessor(ChP); /* start the Rx processor */
2824 Call: sStopRxProcessor(ChP)
2825 CHANNEL_T *ChP; Ptr to channel structure
2839 static void sStopRxProcessor(CHANNEL_T * ChP)
2843 R[0] = ChP->R[0];
2844 R[1] = ChP->R[1];
2846 R[3] = ChP->R[3];
2847 out32(ChP->IndexAddr, R);
2853 Call: sFlushRxFIFO(ChP)
2854 CHANNEL_T *ChP; Ptr to channel structure
2864 static void sFlushRxFIFO(CHANNEL_T * ChP)
2870 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
2874 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
2876 sDisRxFIFO(ChP); /* disable it */
2878 sInB(ChP->IntChan); /* depends on bus i/o timing */
2880 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
2881 Ch = (Byte_t) sGetChanNum(ChP);
2882 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
2883 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
2884 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2885 sOutW(ChP->IndexData, 0);
2886 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2887 sOutW(ChP->IndexData, 0);
2889 sEnRxFIFO(ChP); /* enable Rx FIFO */
2895 Call: sFlushTxFIFO(ChP)
2896 CHANNEL_T *ChP; Ptr to channel structure
2906 static void sFlushTxFIFO(CHANNEL_T * ChP)
2912 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
2916 if (ChP->TxControl[3] & TX_ENABLE) {
2918 sDisTransmit(ChP); /* disable transmitter */
2920 sStopRxProcessor(ChP); /* stop Rx processor */
2922 sInB(ChP->IntChan); /* depends on bus i/o timing */
2923 Ch = (Byte_t) sGetChanNum(ChP);
2924 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
2925 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
2926 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2927 sOutW(ChP->IndexData, 0);
2929 sEnTransmit(ChP); /* enable transmitter */
2930 sStartRxProcessor(ChP); /* restart Rx processor */
2936 Call: sWriteTxPrioByte(ChP,Data)
2937 CHANNEL_T *ChP; Ptr to channel structure
2946 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
2952 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
2953 IndexAddr = ChP->IndexAddr;
2954 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
2955 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
2959 *WordPtr = ChP->TxPrioBuf; /* data byte address */
2964 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
2971 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
2979 Call: sEnInterrupts(ChP,Flags)
2980 CHANNEL_T *ChP; Ptr to channel structure
3008 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3012 ChP->RxControl[2] |=
3015 out32(ChP->IndexAddr, ChP->RxControl);
3017 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3019 out32(ChP->IndexAddr, ChP->TxControl);
3022 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3023 sOutB(ChP->IntMask, Mask);
3030 Call: sDisInterrupts(ChP,Flags)
3031 CHANNEL_T *ChP; Ptr to channel structure
3052 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3056 ChP->RxControl[2] &=
3058 out32(ChP->IndexAddr, ChP->RxControl);
3059 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3060 out32(ChP->IndexAddr, ChP->TxControl);
3063 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3064 sOutB(ChP->IntMask, Mask);
3068 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3070 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);