Lines Matching defs:clear
418 * ignore it if MSI is clear ?
570 * clear delta_msr_wait queue to avoid mem leaks: we may free the irq
1066 unsigned int clear)
1079 if (clear & TIOCM_RTS)
1081 if (clear & TIOCM_DTR)
1241 * XXX It's not clear whether the current behavior is correct
1278 /* clear any pending receive interrupt */
1329 * ever clear. This assumes the UART isn't doing flow
1600 /* clear any pending interrupt */
1608 * and clear RTS and DTR