Lines Matching refs:val
262 u32 val;
269 ret = tb_port_read(out, &val, TB_CFG_PORT,
274 val |= DP_STATUS_CTRL_UF | DP_STATUS_CTRL_CMHS;
276 ret = tb_port_write(out, &val, TB_CFG_PORT,
282 ret = tb_port_read(out, &val, TB_CFG_PORT,
286 if (!(val & DP_STATUS_CTRL_CMHS))
294 static inline u32 tb_dp_cap_get_rate(u32 val)
296 u32 rate = (val & DP_COMMON_CAP_RATE_MASK) >> DP_COMMON_CAP_RATE_SHIFT;
312 static inline u32 tb_dp_cap_set_rate(u32 val, u32 rate)
314 val &= ~DP_COMMON_CAP_RATE_MASK;
320 val |= DP_COMMON_CAP_RATE_RBR << DP_COMMON_CAP_RATE_SHIFT;
323 val |= DP_COMMON_CAP_RATE_HBR << DP_COMMON_CAP_RATE_SHIFT;
326 val |= DP_COMMON_CAP_RATE_HBR2 << DP_COMMON_CAP_RATE_SHIFT;
329 val |= DP_COMMON_CAP_RATE_HBR3 << DP_COMMON_CAP_RATE_SHIFT;
332 return val;
335 static inline u32 tb_dp_cap_get_lanes(u32 val)
337 u32 lanes = (val & DP_COMMON_CAP_LANES_MASK) >> DP_COMMON_CAP_LANES_SHIFT;
351 static inline u32 tb_dp_cap_set_lanes(u32 val, u32 lanes)
353 val &= ~DP_COMMON_CAP_LANES_MASK;
360 val |= DP_COMMON_CAP_1_LANE << DP_COMMON_CAP_LANES_SHIFT;
363 val |= DP_COMMON_CAP_2_LANES << DP_COMMON_CAP_LANES_SHIFT;
366 val |= DP_COMMON_CAP_4_LANES << DP_COMMON_CAP_LANES_SHIFT;
369 return val;
549 u32 val, rate = 0, lanes = 0;
560 ret = tb_port_read(in, &val, TB_CFG_PORT,
565 if (val & DP_COMMON_CAP_DPRX_DONE) {
566 rate = tb_dp_cap_get_rate(val);
567 lanes = tb_dp_cap_get_lanes(val);
580 ret = tb_port_read(in, &val, TB_CFG_PORT,
585 rate = tb_dp_cap_get_rate(val);
586 lanes = tb_dp_cap_get_lanes(val);