Lines Matching refs:ctrl
52 u32 ctrl, lane;
62 ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
73 ctrl |= lane;
75 ctrl |= TB_LC_SX_CTRL_UPSTREAM;
77 ctrl &= ~lane;
79 ctrl &= ~TB_LC_SX_CTRL_UPSTREAM;
82 return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
110 u32 ctrl, lane;
120 ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
131 ctrl |= lane;
133 ctrl &= ~lane;
135 return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
164 u32 ctrl;
171 ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH,
176 ctrl &= ~(TB_LC_SX_CTRL_WOC | TB_LC_SX_CTRL_WOD | TB_LC_SX_CTRL_WOP |
180 ctrl |= TB_LC_SX_CTRL_WOC | TB_LC_SX_CTRL_WOD;
182 ctrl |= TB_LC_SX_CTRL_WOU4;
184 ctrl |= TB_LC_SX_CTRL_WOP;
186 return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, offset + TB_LC_SX_CTRL, 1);
255 u32 ctrl;
257 ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH,
262 ctrl |= TB_LC_SX_CTRL_SLP;
263 ret = tb_sw_write(sw, &ctrl, TB_CFG_SWITCH,