Lines Matching defs:val
196 /* get val from register(r) mask bits(m) */
198 /* set val(v) to mask bits(m) of register(r) */
389 unsigned int val;
391 val = sensor->config->tall << SENSOR_CONFIG0_TALL_SHIFT;
392 writel(val, base + SENSOR_CONFIG0);
394 val = (sensor->config->tsample - 1) << SENSOR_CONFIG1_TSAMPLE_SHIFT;
395 val |= sensor->config->tiddq_en << SENSOR_CONFIG1_TIDDQ_EN_SHIFT;
396 val |= sensor->config->ten_count << SENSOR_CONFIG1_TEN_COUNT_SHIFT;
397 val |= SENSOR_CONFIG1_TEMP_ENABLE;
398 writel(val, base + SENSOR_CONFIG1);
411 static int translate_temp(u16 val)
415 t = ((val & READBACK_VALUE_MASK) >> READBACK_VALUE_SHIFT) * 1000;
416 if (val & READBACK_ADD_HALF)
418 if (val & READBACK_NEGATE)
427 u32 val;
429 val = readl(zone->reg);
430 val = REG_GET_MASK(val, zone->sg->sensor_temp_mask);
431 *out_temp = translate_temp(val);
1620 u32 val;
1627 if (!of_property_read_u32(np_oc, "nvidia,count-threshold", &val)) {
1629 stc->oc_cfg.alarm_cnt_thresh = val;
1632 if (!of_property_read_u32(np_oc, "nvidia,throttle-period-us", &val))
1633 stc->oc_cfg.throt_period = val;
1635 if (!of_property_read_u32(np_oc, "nvidia,alarm-filter", &val))
1636 stc->oc_cfg.alarm_filter = val;
1648 u32 val;
1650 ret = of_property_read_u32(np, "nvidia,priority", &val);
1655 stc->priority = val;
1659 "nvidia,cpu-throt-percent", &val);
1662 val <= TEGRA_SOCTHERM_THROT_LEVEL_HIGH)
1663 stc->cpu_throt_level = val;
1664 else if (!ts->soc->use_ccroc && val <= 100)
1665 stc->cpu_throt_depth = val;
1672 ret = of_property_read_u32(np, "nvidia,gpu-throt-level", &val);
1673 if (!ret && val <= TEGRA_SOCTHERM_THROT_LEVEL_HIGH)
1674 stc->gpu_throt_level = val;