Lines Matching defs:REG_SET_MASK
199 #define REG_SET_MASK(r, m, v) (((r) & ~(m)) | \
488 r = REG_SET_MASK(r, sg->thermtrip_threshold_mask, temp);
489 r = REG_SET_MASK(r, sg->thermtrip_enable_mask, 1);
490 r = REG_SET_MASK(r, sg->thermtrip_any_en_mask, 0);
545 r = REG_SET_MASK(r, sg->thermctl_lvl0_up_thresh_mask, temp);
546 r = REG_SET_MASK(r, sg->thermctl_lvl0_dn_thresh_mask, temp);
547 r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_CPU_THROT_MASK, cpu_throt);
548 r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_GPU_THROT_MASK, gpu_throt);
549 r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 1);
674 r = REG_SET_MASK(r, zn->sg->thermctl_isr_mask, TH_INTR_UP_DN_EN);
686 r = REG_SET_MASK(r, zn->sg->thermctl_isr_mask, 0);
699 r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 0);
706 r = REG_SET_MASK(r, zone->sg->thermctl_lvl0_up_thresh_mask, hi);
707 r = REG_SET_MASK(r, zone->sg->thermctl_lvl0_dn_thresh_mask, lo);
708 r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 1);
957 r = REG_SET_MASK(r, OC_INTR_OC1_MASK, 1);
960 r = REG_SET_MASK(r, OC_INTR_OC2_MASK, 1);
963 r = REG_SET_MASK(r, OC_INTR_OC3_MASK, 1);
966 r = REG_SET_MASK(r, OC_INTR_OC4_MASK, 1);
1795 r = REG_SET_MASK(r, CCROC_THROT_PSKIP_RAMP_DURATION_MASK, 0xff);
1796 r = REG_SET_MASK(r, CCROC_THROT_PSKIP_RAMP_STEP_MASK, 0xf);
1800 r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_ENB_MASK, 1);
1801 r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_DIVIDEND_MASK, dividend);
1802 r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_DIVISOR_MASK, 0xff);
1840 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1);
1841 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT_CPU_MASK, throt_vect);
1842 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT2_CPU_MASK, throt_vect);
1846 r = REG_SET_MASK(0, THROT_PSKIP_RAMP_SEQ_BYPASS_MODE_MASK, 1);
1873 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1);
1874 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_DIVIDEND_MASK, dividend);
1875 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_DIVISOR_MASK, 0xff);
1879 r = REG_SET_MASK(r, THROT_PSKIP_RAMP_DURATION_MASK, 0xff);
1880 r = REG_SET_MASK(r, THROT_PSKIP_RAMP_STEP_MASK, 0xf);
1902 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1);
1903 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT_GPU_MASK, throt_vect);
1916 r = REG_SET_MASK(0, OC1_CFG_HW_RESTORE_MASK, 1);
1917 r = REG_SET_MASK(r, OC1_CFG_THROTTLE_MODE_MASK, oc->mode);
1918 r = REG_SET_MASK(r, OC1_CFG_ALARM_POLARITY_MASK, oc->active_low);
1919 r = REG_SET_MASK(r, OC1_CFG_EN_THROTTLE_MASK, 1);
1957 r = REG_SET_MASK(0, THROT_PRIORITY_LITE_PRIO_MASK, stc.priority);
1960 r = REG_SET_MASK(0, THROT_DELAY_LITE_DELAY_MASK, 0);
1967 r = REG_SET_MASK(0, THROT_PRIORITY_LOCK_PRIORITY_MASK,
1989 v = REG_SET_MASK(0, THROT_GLOBAL_ENB_MASK, 1);
1994 v = REG_SET_MASK(v, CDIVG_USE_THERM_CONTROLS_MASK, 1);
2000 v = REG_SET_MASK(v, CDIVG_USE_THERM_CONTROLS_MASK, 1);
2076 pdiv = REG_SET_MASK(pdiv, ttgs[i]->pdiv_mask,
2081 hotspot = REG_SET_MASK(hotspot,