Lines Matching defs:value
104 u32 value;
110 value = readl_relaxed(sensor->base + DTS_ITENR_OFFSET);
111 value &= ~(LOW_THRESHOLD | HIGH_THRESHOLD);
114 value |= HIGH_THRESHOLD;
117 value |= LOW_THRESHOLD;
120 writel_relaxed(value, sensor->base + DTS_ITENR_OFFSET);
145 u32 value;
148 value = readl_relaxed(sensor->base + DTS_CFGR1_OFFSET);
149 value |= TS1_EN;
150 writel_relaxed(value, sensor->base + DTS_CFGR1_OFFSET);
158 value, (value & TS_RDY),
164 value = readl_relaxed(sensor->base +
166 value |= TS1_START;
167 writel_relaxed(value, sensor->base +
177 u32 value;
182 value = readl_relaxed(sensor->base + DTS_CFGR1_OFFSET);
183 value &= ~TS1_START;
184 writel_relaxed(value, sensor->base + DTS_CFGR1_OFFSET);
190 value = readl_relaxed(sensor->base + DTS_CFGR1_OFFSET);
191 value &= ~TS1_EN;
192 writel_relaxed(value, sensor->base + DTS_CFGR1_OFFSET);
195 return readl_poll_timeout(sensor->base + DTS_SR_OFFSET, value,
196 !(value & TS_RDY),
202 u32 value, clk_freq;
205 /* Figure out prescaler value for PCLK during calibration */
217 value = readl_relaxed(sensor->base + DTS_CFGR1_OFFSET);
220 value &= ~HSREF_CLK_DIV_MASK;
223 value |= (prescaler << HSREF_CLK_DIV_POS);
226 value &= ~REFCLK_SEL;
229 value |= TS1_SMP_TIME_MASK;
232 value &= ~CALIBRATION_CONTROL;
235 value &= ~TS1_INTRIG_SEL_MASK;
236 value |= NO_HW_TRIG;
238 writel_relaxed(value, sensor->base + DTS_CFGR1_OFFSET);
295 u32 value;
298 value = readl_relaxed(sensor->base + DTS_ITENR_OFFSET);
299 value &= ~ITENR_MASK;
300 writel_relaxed(value, sensor->base + DTS_ITENR_OFFSET);