Lines Matching refs:data
140 * struct exynos_tmu_data : A structure to hold the private data of the TMU
154 * @min_efuse_value: minimum valid trimming data
155 * @max_efuse_value: maximum valid trimming data
197 void (*tmu_set_trip_temp)(struct exynos_tmu_data *data, int trip,
199 void (*tmu_set_trip_hyst)(struct exynos_tmu_data *data, int trip,
203 int (*tmu_read)(struct exynos_tmu_data *data);
204 void (*tmu_set_emulation)(struct exynos_tmu_data *data, int temp);
205 void (*tmu_clear_irqs)(struct exynos_tmu_data *data);
212 static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
214 if (data->cal_type == TYPE_ONE_POINT_TRIMMING)
215 return temp + data->temp_error1 - EXYNOS_FIRST_POINT_TRIM;
218 (data->temp_error2 - data->temp_error1) /
220 data->temp_error1;
227 static int code_to_temp(struct exynos_tmu_data *data, u16 temp_code)
229 if (data->cal_type == TYPE_ONE_POINT_TRIMMING)
230 return temp_code - data->temp_error1 + EXYNOS_FIRST_POINT_TRIM;
232 return (temp_code - data->temp_error1) *
234 (data->temp_error2 - data->temp_error1) +
238 static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info)
241 (data->soc == SOC_ARCH_EXYNOS7) ? EXYNOS7_TMU_TEMP_MASK
244 data->temp_error1 = trim_info & tmu_temp_mask;
245 data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) &
248 if (!data->temp_error1 ||
249 (data->min_efuse_value > data->temp_error1) ||
250 (data->temp_error1 > data->max_efuse_value))
251 data->temp_error1 = data->efuse_value & EXYNOS_TMU_TEMP_MASK;
253 if (!data->temp_error2)
254 data->temp_error2 =
255 (data->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) &
261 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
262 struct thermal_zone_device *tzd = data->tzd;
274 if (data->soc != SOC_ARCH_EXYNOS5433) /* FIXME */
282 if (of_thermal_get_ntrips(tzd) > data->ntrip) {
287 (of_thermal_get_ntrips(tzd) - data->ntrip));
290 mutex_lock(&data->lock);
291 clk_enable(data->clk);
292 if (!IS_ERR(data->clk_sec))
293 clk_enable(data->clk_sec);
295 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
300 min_t(int, of_thermal_get_ntrips(tzd), data->ntrip);
302 data->tmu_initialize(pdev);
311 data->tmu_set_trip_temp(data, i, temp);
318 data->tmu_set_trip_hyst(data, i, temp, hyst);
321 data->tmu_clear_irqs(data);
324 clk_disable(data->clk);
325 mutex_unlock(&data->lock);
326 if (!IS_ERR(data->clk_sec))
327 clk_disable(data->clk_sec);
332 static u32 get_con_reg(struct exynos_tmu_data *data, u32 con)
334 if (data->soc == SOC_ARCH_EXYNOS4412 ||
335 data->soc == SOC_ARCH_EXYNOS3250)
339 con |= data->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT;
342 con |= (data->gain << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
352 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
354 mutex_lock(&data->lock);
355 clk_enable(data->clk);
356 data->tmu_control(pdev, on);
357 data->enabled = on;
358 clk_disable(data->clk);
359 mutex_unlock(&data->lock);
362 static void exynos4210_tmu_set_trip_temp(struct exynos_tmu_data *data,
366 of_thermal_get_trip_points(data->tzd);
372 th_code = temp_to_code(data, ref);
373 writeb(th_code, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
377 writeb(temp, data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL0 + trip * 4);
381 static void exynos4210_tmu_set_trip_hyst(struct exynos_tmu_data *data,
388 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
390 sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO));
393 static void exynos4412_tmu_set_trip_temp(struct exynos_tmu_data *data,
398 th = readl(data->base + EXYNOS_THD_TEMP_RISE);
400 th |= temp_to_code(data, temp) << 8 * trip;
401 writel(th, data->base + EXYNOS_THD_TEMP_RISE);
404 con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
406 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
410 static void exynos4412_tmu_set_trip_hyst(struct exynos_tmu_data *data,
415 th = readl(data->base + EXYNOS_THD_TEMP_FALL);
418 th |= temp_to_code(data, temp - hyst) << 8 * trip;
419 writel(th, data->base + EXYNOS_THD_TEMP_FALL);
424 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
427 if (data->soc == SOC_ARCH_EXYNOS3250 ||
428 data->soc == SOC_ARCH_EXYNOS4412 ||
429 data->soc == SOC_ARCH_EXYNOS5250) {
430 if (data->soc == SOC_ARCH_EXYNOS3250) {
431 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1);
433 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1);
435 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2);
437 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2);
441 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO)
442 trim_info = readl(data->base_second + EXYNOS_TMU_REG_TRIMINFO);
444 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
446 sanitize_temp_error(data, trim_info);
449 static void exynos5433_tmu_set_trip_temp(struct exynos_tmu_data *data,
463 th = readl(data->base + reg_off);
465 th |= (temp_to_code(data, temp) << j * 8);
466 writel(th, data->base + reg_off);
469 static void exynos5433_tmu_set_trip_hyst(struct exynos_tmu_data *data,
483 th = readl(data->base + reg_off);
485 th |= (temp_to_code(data, temp - hyst) << j * 8);
486 writel(th, data->base + reg_off);
491 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
495 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
496 sanitize_temp_error(data, trim_info);
504 writel(trim_info, data->base + EXYNOS_TMU_REG_TRIMINFO);
510 data->cal_type = TYPE_TWO_POINT_TRIMMING;
514 data->cal_type = TYPE_ONE_POINT_TRIMMING;
522 static void exynos7_tmu_set_trip_temp(struct exynos_tmu_data *data,
531 th = readl(data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off);
533 th |= temp_to_code(data, temp) << (16 * bit_off);
534 writel(th, data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off);
537 static void exynos7_tmu_set_trip_hyst(struct exynos_tmu_data *data,
546 th = readl(data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off);
548 th |= temp_to_code(data, temp - hyst) << (16 * bit_off);
549 writel(th, data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off);
554 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
557 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
558 sanitize_temp_error(data, trim_info);
563 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
564 struct thermal_zone_device *tz = data->tzd;
567 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
570 for (i = 0; i < data->ntrip; i++) {
578 if (data->soc != SOC_ARCH_EXYNOS4210)
587 writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
588 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
593 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
594 struct thermal_zone_device *tz = data->tzd;
597 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
600 for (i = 0; i < data->ntrip; i++) {
617 writel(pd_det_en, data->base + EXYNOS5433_TMU_PD_DET_EN);
618 writel(interrupt_en, data->base + EXYNOS5433_TMU_REG_INTEN);
619 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
624 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
625 struct thermal_zone_device *tz = data->tzd;
628 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
631 for (i = 0; i < data->ntrip; i++) {
649 writel(interrupt_en, data->base + EXYNOS7_TMU_REG_INTEN);
650 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
655 struct exynos_tmu_data *data = p;
658 if (!data || !data->tmu_read)
660 else if (!data->enabled)
667 mutex_lock(&data->lock);
668 clk_enable(data->clk);
670 value = data->tmu_read(data);
674 *temp = code_to_temp(data, value) * MCELSIUS;
676 clk_disable(data->clk);
677 mutex_unlock(&data->lock);
683 static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val,
691 if (data->soc == SOC_ARCH_EXYNOS7) {
694 val |= (temp_to_code(data, temp) <<
700 val |= (temp_to_code(data, temp) <<
711 static void exynos4412_tmu_set_emulation(struct exynos_tmu_data *data,
717 if (data->soc == SOC_ARCH_EXYNOS5260)
719 else if (data->soc == SOC_ARCH_EXYNOS5433)
721 else if (data->soc == SOC_ARCH_EXYNOS7)
726 val = readl(data->base + emul_con);
727 val = get_emul_con_reg(data, val, temp);
728 writel(val, data->base + emul_con);
733 struct exynos_tmu_data *data = drv_data;
736 if (data->soc == SOC_ARCH_EXYNOS4210)
742 mutex_lock(&data->lock);
743 clk_enable(data->clk);
744 data->tmu_set_emulation(data, temp);
745 clk_disable(data->clk);
746 mutex_unlock(&data->lock);
757 static int exynos4210_tmu_read(struct exynos_tmu_data *data)
759 int ret = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
765 static int exynos4412_tmu_read(struct exynos_tmu_data *data)
767 return readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
770 static int exynos7_tmu_read(struct exynos_tmu_data *data)
772 return readw(data->base + EXYNOS_TMU_REG_CURRENT_TEMP) &
778 struct exynos_tmu_data *data = container_of(work,
781 thermal_zone_device_update(data->tzd, THERMAL_EVENT_UNSPECIFIED);
783 mutex_lock(&data->lock);
784 clk_enable(data->clk);
787 data->tmu_clear_irqs(data);
789 clk_disable(data->clk);
790 mutex_unlock(&data->lock);
791 enable_irq(data->irq);
794 static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data)
799 if (data->soc == SOC_ARCH_EXYNOS5260) {
802 } else if (data->soc == SOC_ARCH_EXYNOS7) {
805 } else if (data->soc == SOC_ARCH_EXYNOS5433) {
813 val_irq = readl(data->base + tmu_intstat);
822 writel(val_irq, data->base + tmu_intclear);
827 struct exynos_tmu_data *data = id;
830 schedule_work(&data->irq_work);
838 .data = (const void *)SOC_ARCH_EXYNOS3250,
841 .data = (const void *)SOC_ARCH_EXYNOS4210,
844 .data = (const void *)SOC_ARCH_EXYNOS4412,
847 .data = (const void *)SOC_ARCH_EXYNOS5250,
850 .data = (const void *)SOC_ARCH_EXYNOS5260,
853 .data = (const void *)SOC_ARCH_EXYNOS5420,
856 .data = (const void *)SOC_ARCH_EXYNOS5420_TRIMINFO,
859 .data = (const void *)SOC_ARCH_EXYNOS5433,
862 .data = (const void *)SOC_ARCH_EXYNOS7,
870 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
873 if (!data || !pdev->dev.of_node)
876 data->id = of_alias_get_id(pdev->dev.of_node, "tmuctrl");
877 if (data->id < 0)
878 data->id = 0;
880 data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
881 if (data->irq <= 0) {
891 data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
892 if (!data->base) {
897 data->soc = (enum soc_type)of_device_get_match_data(&pdev->dev);
899 switch (data->soc) {
901 data->tmu_set_trip_temp = exynos4210_tmu_set_trip_temp;
902 data->tmu_set_trip_hyst = exynos4210_tmu_set_trip_hyst;
903 data->tmu_initialize = exynos4210_tmu_initialize;
904 data->tmu_control = exynos4210_tmu_control;
905 data->tmu_read = exynos4210_tmu_read;
906 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
907 data->ntrip = 4;
908 data->gain = 15;
909 data->reference_voltage = 7;
910 data->efuse_value = 55;
911 data->min_efuse_value = 40;
912 data->max_efuse_value = 100;
920 data->tmu_set_trip_temp = exynos4412_tmu_set_trip_temp;
921 data->tmu_set_trip_hyst = exynos4412_tmu_set_trip_hyst;
922 data->tmu_initialize = exynos4412_tmu_initialize;
923 data->tmu_control = exynos4210_tmu_control;
924 data->tmu_read = exynos4412_tmu_read;
925 data->tmu_set_emulation = exynos4412_tmu_set_emulation;
926 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
927 data->ntrip = 4;
928 data->gain = 8;
929 data->reference_voltage = 16;
930 data->efuse_value = 55;
931 if (data->soc != SOC_ARCH_EXYNOS5420 &&
932 data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO)
933 data->min_efuse_value = 40;
935 data->min_efuse_value = 0;
936 data->max_efuse_value = 100;
939 data->tmu_set_trip_temp = exynos5433_tmu_set_trip_temp;
940 data->tmu_set_trip_hyst = exynos5433_tmu_set_trip_hyst;
941 data->tmu_initialize = exynos5433_tmu_initialize;
942 data->tmu_control = exynos5433_tmu_control;
943 data->tmu_read = exynos4412_tmu_read;
944 data->tmu_set_emulation = exynos4412_tmu_set_emulation;
945 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
946 data->ntrip = 8;
947 data->gain = 8;
949 data->reference_voltage = 23;
951 data->reference_voltage = 16;
952 data->efuse_value = 75;
953 data->min_efuse_value = 40;
954 data->max_efuse_value = 150;
957 data->tmu_set_trip_temp = exynos7_tmu_set_trip_temp;
958 data->tmu_set_trip_hyst = exynos7_tmu_set_trip_hyst;
959 data->tmu_initialize = exynos7_tmu_initialize;
960 data->tmu_control = exynos7_tmu_control;
961 data->tmu_read = exynos7_tmu_read;
962 data->tmu_set_emulation = exynos4412_tmu_set_emulation;
963 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
964 data->ntrip = 8;
965 data->gain = 9;
966 data->reference_voltage = 17;
967 data->efuse_value = 75;
968 data->min_efuse_value = 15;
969 data->max_efuse_value = 100;
976 data->cal_type = TYPE_ONE_POINT_TRIMMING;
982 if (data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO)
990 data->base_second = devm_ioremap(&pdev->dev, res.start,
992 if (!data->base_second) {
1007 struct exynos_tmu_data *data;
1010 data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
1012 if (!data)
1015 platform_set_drvdata(pdev, data);
1016 mutex_init(&data->lock);
1023 data->regulator = devm_regulator_get_optional(&pdev->dev, "vtmu");
1024 if (!IS_ERR(data->regulator)) {
1025 ret = regulator_enable(data->regulator);
1031 if (PTR_ERR(data->regulator) == -EPROBE_DEFER)
1040 INIT_WORK(&data->irq_work, exynos_tmu_work);
1042 data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
1043 if (IS_ERR(data->clk)) {
1045 ret = PTR_ERR(data->clk);
1049 data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif");
1050 if (IS_ERR(data->clk_sec)) {
1051 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) {
1053 ret = PTR_ERR(data->clk_sec);
1057 ret = clk_prepare(data->clk_sec);
1064 ret = clk_prepare(data->clk);
1070 switch (data->soc) {
1073 data->sclk = devm_clk_get(&pdev->dev, "tmu_sclk");
1074 if (IS_ERR(data->sclk)) {
1076 ret = PTR_ERR(data->sclk);
1079 ret = clk_prepare_enable(data->sclk);
1091 * data->tzd must be registered before calling exynos_tmu_initialize(),
1094 data->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, data,
1096 if (IS_ERR(data->tzd)) {
1097 ret = PTR_ERR(data->tzd);
1110 ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
1111 IRQF_TRIGGER_RISING | IRQF_SHARED, dev_name(&pdev->dev), data);
1113 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
1121 thermal_zone_of_sensor_unregister(&pdev->dev, data->tzd);
1123 clk_disable_unprepare(data->sclk);
1125 clk_unprepare(data->clk);
1127 if (!IS_ERR(data->clk_sec))
1128 clk_unprepare(data->clk_sec);
1130 if (!IS_ERR(data->regulator))
1131 regulator_disable(data->regulator);
1138 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
1139 struct thermal_zone_device *tzd = data->tzd;
1144 clk_disable_unprepare(data->sclk);
1145 clk_unprepare(data->clk);
1146 if (!IS_ERR(data->clk_sec))
1147 clk_unprepare(data->clk_sec);
1149 if (!IS_ERR(data->regulator))
1150 regulator_disable(data->regulator);