Lines Matching defs:tmu
64 struct imx8mm_tmu *tmu = sensor->priv;
67 val = readl_relaxed(tmu->base + TRITSR) & TRITSR_TEMP0_VAL_MASK;
84 struct imx8mm_tmu *tmu = sensor->priv;
88 val = readl_relaxed(tmu->base + TRITSR);
108 struct imx8mm_tmu *tmu = sensor->priv;
110 return tmu->socdata->get_temp(data, temp);
117 static void imx8mm_tmu_enable(struct imx8mm_tmu *tmu, bool enable)
121 val = readl_relaxed(tmu->base + TER);
123 if (tmu->socdata->version == TMU_VER2)
125 writel_relaxed(val, tmu->base + TER);
128 static void imx8mm_tmu_probe_sel_all(struct imx8mm_tmu *tmu)
132 val = readl_relaxed(tmu->base + TPS);
134 writel_relaxed(val, tmu->base + TPS);
140 struct imx8mm_tmu *tmu;
146 tmu = devm_kzalloc(&pdev->dev, struct_size(tmu, sensors,
148 if (!tmu)
151 tmu->socdata = data;
153 tmu->base = devm_platform_ioremap_resource(pdev, 0);
154 if (IS_ERR(tmu->base))
155 return PTR_ERR(tmu->base);
157 tmu->clk = devm_clk_get(&pdev->dev, NULL);
158 if (IS_ERR(tmu->clk))
159 return dev_err_probe(&pdev->dev, PTR_ERR(tmu->clk),
160 "failed to get tmu clock\n");
162 ret = clk_prepare_enable(tmu->clk);
164 dev_err(&pdev->dev, "failed to enable tmu clock: %d\n", ret);
169 imx8mm_tmu_enable(tmu, false);
172 tmu->sensors[i].priv = tmu;
173 tmu->sensors[i].tzd =
175 &tmu->sensors[i],
177 if (IS_ERR(tmu->sensors[i].tzd)) {
181 return PTR_ERR(tmu->sensors[i].tzd);
183 tmu->sensors[i].hw_id = i;
186 platform_set_drvdata(pdev, tmu);
189 if (tmu->socdata->version == TMU_VER2)
190 imx8mm_tmu_probe_sel_all(tmu);
193 imx8mm_tmu_enable(tmu, true);
200 struct imx8mm_tmu *tmu = platform_get_drvdata(pdev);
203 imx8mm_tmu_enable(tmu, false);
205 clk_disable_unprepare(tmu->clk);
224 { .compatible = "fsl,imx8mm-tmu", .data = &imx8mm_tmu_data, },
225 { .compatible = "fsl,imx8mp-tmu", .data = &imx8mp_tmu_data, },