Lines Matching defs:config_reg
270 u32 config_reg;
292 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
293 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
295 config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK;
297 config_reg &= ~GQSPI_CFG_ENDIAN_MASK;
299 config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK;
301 config_reg |= GQSPI_CFG_WP_HOLD_MASK;
303 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
305 config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;
307 config_reg &= ~GQSPI_CFG_CLK_POL_MASK;
308 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
451 u32 config_reg, baud_rate_val = 0;
462 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
465 config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK);
468 config_reg |= GQSPI_CFG_CLK_PHA_MASK;
470 config_reg |= GQSPI_CFG_CLK_POL_MASK;
472 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
473 config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
474 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
637 u32 config_reg, genfifoentry;
651 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
652 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
653 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
736 u32 rx_bytes, rx_rem, config_reg;
743 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
744 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
745 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
770 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
771 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
772 config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;
773 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
796 u32 config_reg;
801 config_reg = zynqmp_gqspi_read(xqspi,
803 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
805 config_reg);