Lines Matching refs:master
29 struct spi_master *master;
130 struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
183 struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
201 struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
220 struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
336 struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
349 static bool uniphier_spi_can_dma(struct spi_master *master,
353 struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
356 if ((!master->dma_tx && !master->dma_rx)
357 || (!master->dma_tx && t->tx_buf)
358 || (!master->dma_rx && t->rx_buf))
366 struct spi_master *master = data;
367 struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
373 spi_finalize_current_transfer(master);
378 struct spi_master *master = data;
379 struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
385 spi_finalize_current_transfer(master);
388 static int uniphier_spi_transfer_one_dma(struct spi_master *master,
392 struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
415 dmaengine_slave_config(master->dma_rx, &rxconf);
418 master->dma_rx,
425 rxdesc->callback_param = master;
431 dma_async_issue_pending(master->dma_rx);
442 dmaengine_slave_config(master->dma_tx, &txconf);
445 master->dma_tx,
452 txdesc->callback_param = master;
458 dma_async_issue_pending(master->dma_tx);
466 dmaengine_terminate_sync(master->dma_rx);
471 static int uniphier_spi_transfer_one_irq(struct spi_master *master,
475 struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
476 struct device *dev = master->dev.parent;
498 static int uniphier_spi_transfer_one_poll(struct spi_master *master,
502 struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
523 return uniphier_spi_transfer_one_irq(master, spi, t);
526 static int uniphier_spi_transfer_one(struct spi_master *master,
530 struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
540 use_dma = master->can_dma ? master->can_dma(master, spi, t) : false;
542 return uniphier_spi_transfer_one_dma(master, spi, t);
551 return uniphier_spi_transfer_one_irq(master, spi, t);
553 return uniphier_spi_transfer_one_poll(master, spi, t);
556 static int uniphier_spi_prepare_transfer_hardware(struct spi_master *master)
558 struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
565 static int uniphier_spi_unprepare_transfer_hardware(struct spi_master *master)
567 struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
574 static void uniphier_spi_handle_err(struct spi_master *master,
577 struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
590 dmaengine_terminate_async(master->dma_tx);
595 dmaengine_terminate_async(master->dma_rx);
644 struct spi_master *master;
652 master = spi_alloc_master(&pdev->dev, sizeof(*priv));
653 if (!master)
656 platform_set_drvdata(pdev, master);
658 priv = spi_master_get_devdata(master);
659 priv->master = master;
697 master->max_speed_hz = DIV_ROUND_UP(clk_rate, SSI_MIN_CLK_DIVIDER);
698 master->min_speed_hz = DIV_ROUND_UP(clk_rate, SSI_MAX_CLK_DIVIDER);
699 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
700 master->dev.of_node = pdev->dev.of_node;
701 master->bus_num = pdev->id;
702 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
704 master->set_cs = uniphier_spi_set_cs;
705 master->transfer_one = uniphier_spi_transfer_one;
706 master->prepare_transfer_hardware
708 master->unprepare_transfer_hardware
710 master->handle_err = uniphier_spi_handle_err;
711 master->can_dma = uniphier_spi_can_dma;
713 master->num_chipselect = 1;
714 master->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
716 master->dma_tx = dma_request_chan(&pdev->dev, "tx");
717 if (IS_ERR_OR_NULL(master->dma_tx)) {
718 if (PTR_ERR(master->dma_tx) == -EPROBE_DEFER) {
722 master->dma_tx = NULL;
725 ret = dma_get_slave_caps(master->dma_tx, &caps);
734 master->dma_rx = dma_request_chan(&pdev->dev, "rx");
735 if (IS_ERR_OR_NULL(master->dma_rx)) {
736 if (PTR_ERR(master->dma_rx) == -EPROBE_DEFER) {
740 master->dma_rx = NULL;
743 ret = dma_get_slave_caps(master->dma_rx, &caps);
752 master->max_dma_len = min(dma_tx_burst, dma_rx_burst);
754 ret = devm_spi_register_master(&pdev->dev, master);
761 if (!IS_ERR_OR_NULL(master->dma_rx)) {
762 dma_release_channel(master->dma_rx);
763 master->dma_rx = NULL;
765 if (!IS_ERR_OR_NULL(master->dma_tx)) {
766 dma_release_channel(master->dma_tx);
767 master->dma_tx = NULL;
774 spi_master_put(master);
780 struct spi_master *master = platform_get_drvdata(pdev);
781 struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
783 if (master->dma_tx)
784 dma_release_channel(master->dma_tx);
785 if (master->dma_rx)
786 dma_release_channel(master->dma_rx);