Lines Matching refs:master
126 * @master: Pointer to the SPI master structure
163 struct spi_master *master;
218 * @master: Pointer to struct spi_master.
222 static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val)
224 struct pch_spi_data *data = spi_master_get_devdata(master);
230 * @master: Pointer to struct spi_master.
233 static inline u32 pch_spi_readreg(struct spi_master *master, int idx)
235 struct pch_spi_data *data = spi_master_get_devdata(master);
239 static inline void pch_spi_setclr_reg(struct spi_master *master, int idx,
242 u32 tmp = pch_spi_readreg(master, idx);
244 pch_spi_writereg(master, idx, tmp);
247 static void pch_spi_set_master_mode(struct spi_master *master)
249 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0);
254 * @master: Pointer to struct spi_master.
256 static void pch_spi_clear_fifo(struct spi_master *master)
258 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0);
259 pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT);
314 pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
323 dev_vdbg(&data->master->dev,
385 * @master: Pointer to struct spi_master.
388 static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz)
396 pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS);
401 * @master: Pointer to struct spi_master.
404 static void pch_spi_set_bits_per_word(struct spi_master *master,
408 pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT);
410 pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0);
422 __func__, pch_spi_readreg(spi->master, PCH_SPBRR),
424 pch_spi_set_baud_rate(spi->master, spi->max_speed_hz);
427 pch_spi_set_bits_per_word(spi->master, spi->bits_per_word);
435 pch_spi_setclr_reg(spi->master, PCH_SPCR, flags,
439 pch_spi_clear_fifo(spi->master);
444 * @master: Pointer to struct spi_master.
446 static void pch_spi_reset(struct spi_master *master)
449 pch_spi_writereg(master, PCH_SRST, 0x1);
452 pch_spi_writereg(master, PCH_SRST, 0x0);
459 struct pch_spi_data *data = spi_master_get_devdata(pspi->master);
555 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
556 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
562 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
563 pch_spi_set_bits_per_word(data->master,
621 dev_dbg(&data->master->dev,
624 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
627 pch_spi_writereg(data->master, PCH_SPDWR, data->pkt_tx_buff[j]);
640 dev_dbg(&data->master->dev, "%s called\n", __func__);
646 dev_dbg(&data->master->dev,
654 dev_dbg(&data->master->dev,
669 dev_dbg(&data->master->dev, "%s:Invoke queue_work\n", __func__);
673 dev_dbg(&data->master->dev,
693 pch_spi_setclr_reg(data->master, PCH_SPCR,
700 pch_spi_setclr_reg(data->master, PCH_SPCR,
708 dev_dbg(&data->master->dev,
714 pch_spi_writereg(data->master, PCH_SPSR,
715 pch_spi_readreg(data->master, PCH_SPSR));
717 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT);
719 pch_spi_clear_fifo(data->master);
781 pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL);
787 dev_dbg(&data->master->dev,
793 dev_err(&data->master->dev,
796 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent,
799 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_tx_p, dma->nent,
811 pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
815 pch_spi_writereg(data->master, PCH_SPSR,
816 pch_spi_readreg(data->master, PCH_SPSR));
818 pch_spi_clear_fifo(data->master);
877 dev_err(&data->master->dev,
892 dev_err(&data->master->dev,
938 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
940 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
948 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
950 pch_spi_set_bits_per_word(data->master,
994 dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n",
999 pch_spi_setclr_reg(data->master, PCH_SPCR,
1041 dev_err(&data->master->dev,
1045 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE);
1103 dev_err(&data->master->dev,
1107 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE);
1113 dev_dbg(&data->master->dev, "%s:Pulling down SSN low - writing 0x2 to SSNXCR\n", __func__);
1116 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
1132 dev_dbg(&data->master->dev, "%s data initialized\n", __func__);
1137 dev_dbg(&data->master->dev,
1157 dev_dbg(&data->master->dev,
1175 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL);
1186 dev_dbg(&data->master->dev,
1193 dev_dbg(&data->master->dev,
1234 dev_dbg(&data->master->dev,
1253 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_HIGH);
1272 pch_spi_reset(data->master);
1321 struct spi_master *master;
1327 master = spi_alloc_master(&board_dat->pdev->dev,
1329 if (!master) {
1335 data = spi_master_get_devdata(master);
1336 data->master = master;
1354 /* initialize members of SPI master */
1355 master->num_chipselect = PCH_MAX_CS;
1356 master->transfer = pch_spi_transfer;
1357 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1358 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
1359 master->max_speed_hz = PCH_MAX_BAUDRATE;
1388 pch_spi_set_master_mode(master);
1397 ret = spi_register_master(master);
1414 spi_master_put(master);
1450 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1456 spi_unregister_master(data->master);
1488 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1489 pch_spi_reset(data->master);
1523 pch_spi_reset(data->master);
1524 pch_spi_set_master_mode(data->master);