Lines Matching defs:qspi
128 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
131 return readl(qspi->base + reg);
134 static inline void ti_qspi_write(struct ti_qspi *qspi,
137 writel(val, qspi->base + reg);
142 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
143 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
148 dev_dbg(qspi->dev, "master busy doing other transfers\n");
152 if (!qspi->spi_max_frequency) {
153 dev_err(qspi->dev, "spi max frequency not defined\n");
157 clk_rate = clk_get_rate(qspi->fclk);
159 clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
162 dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
167 dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
172 dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
173 qspi->spi_max_frequency, clk_div);
175 ret = pm_runtime_get_sync(qspi->dev);
177 pm_runtime_put_noidle(qspi->dev);
178 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
182 clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
187 ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
191 ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
194 pm_runtime_mark_last_busy(qspi->dev);
195 ret = pm_runtime_put_autosuspend(qspi->dev);
197 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
204 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
206 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
208 ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
211 static inline u32 qspi_is_busy(struct ti_qspi *qspi)
216 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
219 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
222 WARN(stat & BUSY, "qspi busy\n");
226 static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
232 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
238 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
244 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t,
253 cmd = qspi->cmd | QSPI_WR_SNGL;
258 if (qspi_is_busy(qspi))
263 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
264 cmd, qspi->dc, *txbuf);
269 writel(data, qspi->base +
272 writel(data, qspi->base +
275 writel(data, qspi->base +
278 writel(data, qspi->base +
283 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
284 cmd = qspi->cmd | QSPI_WR_SNGL;
290 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
291 cmd, qspi->dc, *txbuf);
292 writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
295 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
296 cmd, qspi->dc, *txbuf);
297 writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
301 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
302 if (ti_qspi_poll_wc(qspi)) {
303 dev_err(qspi->dev, "write timed out\n");
313 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t,
323 cmd = qspi->cmd;
339 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
340 if (qspi_is_busy(qspi))
363 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
364 if (ti_qspi_poll_wc(qspi)) {
365 dev_err(qspi->dev, "read timed out\n");
377 rx = readl(qspi->base + QSPI_SPI_DATA_REG_3);
379 rx = readl(qspi->base + QSPI_SPI_DATA_REG_2);
381 rx = readl(qspi->base + QSPI_SPI_DATA_REG_1);
383 rx = readl(qspi->base + QSPI_SPI_DATA_REG);
387 rx = readl(qspi->base + QSPI_SPI_DATA_REG);
399 *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
402 *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
412 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t,
418 ret = qspi_write_msg(qspi, t, count);
420 dev_dbg(qspi->dev, "Error while writing\n");
426 ret = qspi_read_msg(qspi, t, count);
428 dev_dbg(qspi->dev, "Error while reading\n");
438 struct ti_qspi *qspi = param;
440 complete(&qspi->transfer_complete);
443 static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst,
446 struct dma_chan *chan = qspi->rx_chan;
455 dev_err(qspi->dev, "device_prep_dma_memcpy error\n");
460 tx->callback_param = qspi;
462 reinit_completion(&qspi->transfer_complete);
466 dev_err(qspi->dev, "dma_submit_error %d\n", cookie);
471 time_left = wait_for_completion_timeout(&qspi->transfer_complete,
475 dev_err(qspi->dev, "DMA wait_for_completion_timeout\n");
482 static int ti_qspi_dma_bounce_buffer(struct ti_qspi *qspi, loff_t offs,
485 dma_addr_t dma_src = qspi->mmap_phys_base + offs;
496 ret = ti_qspi_dma_xfer(qspi, qspi->rx_bb_dma_addr,
500 memcpy(to, qspi->rx_bb_addr, xfer_len);
509 static int ti_qspi_dma_xfer_sg(struct ti_qspi *qspi, struct sg_table rx_sg,
513 dma_addr_t dma_src = qspi->mmap_phys_base + from;
520 ret = ti_qspi_dma_xfer(qspi, dma_dst, dma_src, len);
531 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
533 ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
534 if (qspi->ctrl_base) {
535 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
539 qspi->mmap_enabled = true;
540 qspi->current_cs = spi->chip_select;
545 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
547 ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
548 if (qspi->ctrl_base)
549 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
551 qspi->mmap_enabled = false;
552 qspi->current_cs = -1;
559 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
575 ti_qspi_write(qspi, memval,
581 struct ti_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
585 if (op->addr.val < qspi->mmap_size) {
587 if (op->addr.val + op->data.nbytes > qspi->mmap_size) {
588 max_len = qspi->mmap_size - op->addr.val;
611 struct ti_qspi *qspi = spi_master_get_devdata(mem->spi->master);
622 if (from + op->data.nbytes > qspi->mmap_size)
625 mutex_lock(&qspi->list_lock);
627 if (!qspi->mmap_enabled || qspi->current_cs != mem->spi->chip_select)
632 if (qspi->rx_chan) {
638 ret = ti_qspi_dma_xfer_sg(qspi, sgt, from);
642 ret = ti_qspi_dma_bounce_buffer(qspi, from,
647 memcpy_fromio(op->data.buf.in, qspi->mmap_base + from,
651 mutex_unlock(&qspi->list_lock);
664 struct ti_qspi *qspi = spi_master_get_devdata(master);
672 qspi->dc = 0;
675 qspi->dc |= QSPI_CKPHA(spi->chip_select);
677 qspi->dc |= QSPI_CKPOL(spi->chip_select);
679 qspi->dc |= QSPI_CSPOL(spi->chip_select);
687 qspi->cmd = 0;
688 qspi->cmd |= QSPI_EN_CS(spi->chip_select);
689 qspi->cmd |= QSPI_FLEN(frame_len_words);
691 ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
693 mutex_lock(&qspi->list_lock);
695 if (qspi->mmap_enabled)
699 qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) |
705 ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen);
707 dev_dbg(qspi->dev, "transfer message failed\n");
708 mutex_unlock(&qspi->list_lock);
718 mutex_unlock(&qspi->list_lock);
720 ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
729 struct ti_qspi *qspi;
731 qspi = dev_get_drvdata(dev);
732 ti_qspi_restore_ctx(qspi);
737 static void ti_qspi_dma_cleanup(struct ti_qspi *qspi)
739 if (qspi->rx_bb_addr)
740 dma_free_coherent(qspi->dev, QSPI_DMA_BUFFER_SIZE,
741 qspi->rx_bb_addr,
742 qspi->rx_bb_dma_addr);
744 if (qspi->rx_chan)
745 dma_release_channel(qspi->rx_chan);
749 {.compatible = "ti,dra7xxx-qspi" },
750 {.compatible = "ti,am4372-qspi" },
757 struct ti_qspi *qspi;
765 master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
783 qspi = spi_master_get_devdata(master);
784 qspi->master = master;
785 qspi->dev = &pdev->dev;
786 platform_set_drvdata(pdev, qspi);
809 qspi->mmap_size = resource_size(res_mmap);
817 mutex_init(&qspi->list_lock);
819 qspi->base = devm_ioremap_resource(&pdev->dev, r);
820 if (IS_ERR(qspi->base)) {
821 ret = PTR_ERR(qspi->base);
827 qspi->ctrl_base =
830 if (IS_ERR(qspi->ctrl_base)) {
831 ret = PTR_ERR(qspi->ctrl_base);
836 1, &qspi->ctrl_reg);
844 qspi->fclk = devm_clk_get(&pdev->dev, "fck");
845 if (IS_ERR(qspi->fclk)) {
846 ret = PTR_ERR(qspi->fclk);
855 qspi->spi_max_frequency = max_freq;
860 qspi->rx_chan = dma_request_chan_by_mask(&mask);
861 if (IS_ERR(qspi->rx_chan)) {
862 dev_err(qspi->dev,
864 qspi->rx_chan = NULL;
868 qspi->rx_bb_addr = dma_alloc_coherent(qspi->dev,
870 &qspi->rx_bb_dma_addr,
872 if (!qspi->rx_bb_addr) {
873 dev_err(qspi->dev,
875 dma_release_channel(qspi->rx_chan);
878 master->dma_rx = qspi->rx_chan;
879 init_completion(&qspi->transfer_complete);
881 qspi->mmap_phys_base = (dma_addr_t)res_mmap->start;
884 if (!qspi->rx_chan && res_mmap) {
885 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
886 if (IS_ERR(qspi->mmap_base)) {
889 PTR_ERR(qspi->mmap_base));
890 qspi->mmap_base = NULL;
894 qspi->mmap_enabled = false;
895 qspi->current_cs = -1;
901 ti_qspi_dma_cleanup(qspi);
911 struct ti_qspi *qspi = platform_get_drvdata(pdev);
914 rc = spi_master_suspend(qspi->master);
921 ti_qspi_dma_cleanup(qspi);
934 .name = "ti-qspi",
945 MODULE_ALIAS("platform:ti-qspi");