Lines Matching refs:tsd
139 static inline u32 tegra_sflash_readl(struct tegra_sflash_data *tsd,
142 return readl(tsd->base + reg);
145 static inline void tegra_sflash_writel(struct tegra_sflash_data *tsd,
148 writel(val, tsd->base + reg);
151 static void tegra_sflash_clear_status(struct tegra_sflash_data *tsd)
154 tegra_sflash_writel(tsd, SPI_RDY | SPI_FIFO_ERROR, SPI_STATUS);
158 struct spi_device *spi, struct tegra_sflash_data *tsd,
161 unsigned remain_len = t->len - tsd->cur_pos;
164 tsd->bytes_per_word = DIV_ROUND_UP(t->bits_per_word, 8);
165 max_word = remain_len / tsd->bytes_per_word;
168 tsd->curr_xfer_words = max_word;
173 struct tegra_sflash_data *tsd, struct spi_transfer *t)
177 unsigned max_n_32bit = tsd->curr_xfer_words;
178 u8 *tx_buf = (u8 *)t->tx_buf + tsd->cur_tx_pos;
182 nbytes = max_n_32bit * tsd->bytes_per_word;
184 status = tegra_sflash_readl(tsd, SPI_STATUS);
189 for (i = 0; nbytes && (i < tsd->bytes_per_word);
192 tegra_sflash_writel(tsd, x, SPI_TX_FIFO);
196 status = tegra_sflash_readl(tsd, SPI_STATUS);
198 tsd->cur_tx_pos += max_n_32bit * tsd->bytes_per_word;
203 struct tegra_sflash_data *tsd, struct spi_transfer *t)
207 u8 *rx_buf = (u8 *)t->rx_buf + tsd->cur_rx_pos;
209 status = tegra_sflash_readl(tsd, SPI_STATUS);
212 u32 x = tegra_sflash_readl(tsd, SPI_RX_FIFO);
214 for (i = 0; (i < tsd->bytes_per_word); i++)
217 status = tegra_sflash_readl(tsd, SPI_STATUS);
219 tsd->cur_rx_pos += read_words * tsd->bytes_per_word;
224 struct tegra_sflash_data *tsd, struct spi_transfer *t)
229 if (tsd->cur_direction & DATA_DIR_TX)
232 if (tsd->cur_direction & DATA_DIR_RX)
235 tegra_sflash_writel(tsd, val, SPI_DMA_CTL);
236 tsd->dma_control_reg = val;
238 if (tsd->cur_direction & DATA_DIR_TX)
239 cur_words = tegra_sflash_fill_tx_fifo_from_client_txbuf(tsd, t);
241 cur_words = tsd->curr_xfer_words;
243 tegra_sflash_writel(tsd, val, SPI_DMA_CTL);
244 tsd->dma_control_reg = val;
246 tegra_sflash_writel(tsd, val, SPI_DMA_CTL);
254 struct tegra_sflash_data *tsd = spi_master_get_devdata(spi->master);
259 if (speed != tsd->cur_speed) {
260 clk_set_rate(tsd->clk, speed);
261 tsd->cur_speed = speed;
264 tsd->cur_spi = spi;
265 tsd->cur_pos = 0;
266 tsd->cur_rx_pos = 0;
267 tsd->cur_tx_pos = 0;
268 tsd->curr_xfer = t;
269 tegra_sflash_calculate_curr_xfer_param(spi, tsd, t);
271 command = tsd->def_command_reg;
285 command = tsd->command_reg;
291 tsd->cur_direction = 0;
294 tsd->cur_direction |= DATA_DIR_RX;
298 tsd->cur_direction |= DATA_DIR_TX;
300 tegra_sflash_writel(tsd, command, SPI_COMMAND);
301 tsd->command_reg = command;
303 return tegra_sflash_start_cpu_based_transfer(tsd, t);
311 struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
320 reinit_completion(&tsd->xfer_completion);
324 dev_err(tsd->dev,
329 ret = wait_for_completion_timeout(&tsd->xfer_completion,
332 dev_err(tsd->dev,
338 if (tsd->tx_status || tsd->rx_status) {
339 dev_err(tsd->dev, "Error in Transfer\n");
346 tegra_sflash_writel(tsd, tsd->def_command_reg,
353 tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND);
359 static irqreturn_t handle_cpu_based_xfer(struct tegra_sflash_data *tsd)
361 struct spi_transfer *t = tsd->curr_xfer;
363 spin_lock(&tsd->lock);
364 if (tsd->tx_status || tsd->rx_status || (tsd->status_reg & SPI_BSY)) {
365 dev_err(tsd->dev,
366 "CpuXfer ERROR bit set 0x%x\n", tsd->status_reg);
367 dev_err(tsd->dev,
368 "CpuXfer 0x%08x:0x%08x\n", tsd->command_reg,
369 tsd->dma_control_reg);
370 reset_control_assert(tsd->rst);
372 reset_control_deassert(tsd->rst);
373 complete(&tsd->xfer_completion);
377 if (tsd->cur_direction & DATA_DIR_RX)
378 tegra_sflash_read_rx_fifo_to_client_rxbuf(tsd, t);
380 if (tsd->cur_direction & DATA_DIR_TX)
381 tsd->cur_pos = tsd->cur_tx_pos;
383 tsd->cur_pos = tsd->cur_rx_pos;
385 if (tsd->cur_pos == t->len) {
386 complete(&tsd->xfer_completion);
390 tegra_sflash_calculate_curr_xfer_param(tsd->cur_spi, tsd, t);
391 tegra_sflash_start_cpu_based_transfer(tsd, t);
393 spin_unlock(&tsd->lock);
399 struct tegra_sflash_data *tsd = context_data;
401 tsd->status_reg = tegra_sflash_readl(tsd, SPI_STATUS);
402 if (tsd->cur_direction & DATA_DIR_TX)
403 tsd->tx_status = tsd->status_reg & SPI_TX_OVF;
405 if (tsd->cur_direction & DATA_DIR_RX)
406 tsd->rx_status = tsd->status_reg & SPI_RX_UNF;
407 tegra_sflash_clear_status(tsd);
409 return handle_cpu_based_xfer(tsd);
421 struct tegra_sflash_data *tsd;
431 master = spi_alloc_master(&pdev->dev, sizeof(*tsd));
444 tsd = spi_master_get_devdata(master);
445 tsd->master = master;
446 tsd->dev = &pdev->dev;
447 spin_lock_init(&tsd->lock);
449 if (of_property_read_u32(tsd->dev->of_node, "spi-max-frequency",
453 tsd->base = devm_platform_ioremap_resource(pdev, 0);
454 if (IS_ERR(tsd->base)) {
455 ret = PTR_ERR(tsd->base);
462 tsd->irq = ret;
464 ret = request_irq(tsd->irq, tegra_sflash_isr, 0,
465 dev_name(&pdev->dev), tsd);
468 tsd->irq);
472 tsd->clk = devm_clk_get(&pdev->dev, NULL);
473 if (IS_ERR(tsd->clk)) {
475 ret = PTR_ERR(tsd->clk);
479 tsd->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi");
480 if (IS_ERR(tsd->rst)) {
482 ret = PTR_ERR(tsd->rst);
486 init_completion(&tsd->xfer_completion);
502 reset_control_assert(tsd->rst);
504 reset_control_deassert(tsd->rst);
506 tsd->def_command_reg = SPI_M_S | SPI_CS_SW;
507 tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND);
523 free_irq(tsd->irq, tsd);
532 struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
534 free_irq(tsd->irq, tsd);
554 struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
563 tegra_sflash_writel(tsd, tsd->command_reg, SPI_COMMAND);
573 struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
576 tegra_sflash_readl(tsd, SPI_COMMAND);
578 clk_disable_unprepare(tsd->clk);
585 struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
588 ret = clk_prepare_enable(tsd->clk);
590 dev_err(tsd->dev, "clk_prepare failed: %d\n", ret);