Lines Matching refs:status
247 /* Write 1 to clear status register */
251 /* Clear fifo status error if any */
514 u32 status;
516 status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
517 if ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
518 status |= SPI_RX_FIFO_FLUSH | SPI_TX_FIFO_FLUSH;
519 tegra_spi_writel(tspi, status, SPI_FIFO_STATUS);
520 while ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
521 status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
1045 msg->status = 0;
1121 msg->status = ret;