Lines Matching defs:sspi
141 static int read_fifo(struct synquacer_spi *sspi)
143 u32 len = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMSTATUS);
147 len = min(len, sspi->rx_words);
149 switch (sspi->bpw) {
151 u8 *buf = sspi->rx_buf;
153 ioread8_rep(sspi->regs + SYNQUACER_HSSPI_REG_RX_FIFO,
155 sspi->rx_buf = buf + len;
159 u16 *buf = sspi->rx_buf;
161 ioread16_rep(sspi->regs + SYNQUACER_HSSPI_REG_RX_FIFO,
163 sspi->rx_buf = buf + len;
169 u32 *buf = sspi->rx_buf;
171 ioread32_rep(sspi->regs + SYNQUACER_HSSPI_REG_RX_FIFO,
173 sspi->rx_buf = buf + len;
180 sspi->rx_words -= len;
184 static int write_fifo(struct synquacer_spi *sspi)
186 u32 len = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMSTATUS);
191 sspi->tx_words);
193 switch (sspi->bpw) {
195 const u8 *buf = sspi->tx_buf;
197 iowrite8_rep(sspi->regs + SYNQUACER_HSSPI_REG_TX_FIFO,
199 sspi->tx_buf = buf + len;
203 const u16 *buf = sspi->tx_buf;
205 iowrite16_rep(sspi->regs + SYNQUACER_HSSPI_REG_TX_FIFO,
207 sspi->tx_buf = buf + len;
213 const u32 *buf = sspi->tx_buf;
215 iowrite32_rep(sspi->regs + SYNQUACER_HSSPI_REG_TX_FIFO,
217 sspi->tx_buf = buf + len;
224 sspi->tx_words -= len;
232 struct synquacer_spi *sspi = spi_master_get_devdata(master);
239 dev_err(sspi->dev,
258 if (speed == sspi->speed &&
259 bus_width == sspi->bus_width && bpw == sspi->bpw &&
260 mode == sspi->mode && cs == sspi->cs &&
261 transfer_mode == sspi->transfer_mode) {
265 sspi->transfer_mode = transfer_mode;
270 dev_err(sspi->dev, "Requested rate too low (%u)\n",
271 sspi->speed);
275 val = readl(sspi->regs + SYNQUACER_HSSPI_REG_PCC(cs));
304 if (sspi->aces)
309 if (sspi->rtm)
321 writel(val, sspi->regs + SYNQUACER_HSSPI_REG_PCC(cs));
323 val = readl(sspi->regs + SYNQUACER_HSSPI_REG_FIFOCFG);
327 writel(val, sspi->regs + SYNQUACER_HSSPI_REG_FIFOCFG);
329 val = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMSTART);
342 writel(val, sspi->regs + SYNQUACER_HSSPI_REG_DMSTART);
344 sspi->bpw = bpw;
345 sspi->mode = mode;
346 sspi->speed = speed;
347 sspi->cs = spi->chip_select;
348 sspi->bus_width = bus_width;
357 struct synquacer_spi *sspi = spi_master_get_devdata(master);
364 val = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMSTART);
366 writel(val, sspi->regs + SYNQUACER_HSSPI_REG_DMSTART);
368 val = readl(sspi->regs + SYNQUACER_HSSPI_REG_FIFOCFG);
371 writel(val, sspi->regs + SYNQUACER_HSSPI_REG_FIFOCFG);
389 reinit_completion(&sspi->transfer_done);
391 sspi->tx_buf = xfer->tx_buf;
392 sspi->rx_buf = xfer->rx_buf;
394 switch (sspi->bpw) {
407 dev_err(sspi->dev, "unsupported bpw: %d\n", sspi->bpw);
412 sspi->tx_words = words;
414 sspi->tx_words = 0;
417 sspi->rx_words = words;
419 sspi->rx_words = 0;
422 status = write_fifo(sspi);
424 dev_err(sspi->dev, "failed write_fifo. status: 0x%x\n",
431 val = readl(sspi->regs + SYNQUACER_HSSPI_REG_FIFOCFG);
434 val |= ((sspi->rx_words > SYNQUACER_HSSPI_FIFO_DEPTH ?
435 SYNQUACER_HSSPI_FIFO_RX_THRESHOLD : sspi->rx_words) <<
437 writel(val, sspi->regs + SYNQUACER_HSSPI_REG_FIFOCFG);
440 writel(~0, sspi->regs + SYNQUACER_HSSPI_REG_TXC);
441 writel(~0, sspi->regs + SYNQUACER_HSSPI_REG_RXC);
444 val = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMSTART);
446 writel(val, sspi->regs + SYNQUACER_HSSPI_REG_DMSTART);
450 writel(val, sspi->regs + SYNQUACER_HSSPI_REG_TXE);
451 status = wait_for_completion_timeout(&sspi->transfer_done,
453 writel(0, sspi->regs + SYNQUACER_HSSPI_REG_TXE);
461 writel(val, sspi->regs + SYNQUACER_HSSPI_REG_RXE);
462 status = wait_for_completion_timeout(&sspi->transfer_done,
464 writel(0, sspi->regs + SYNQUACER_HSSPI_REG_RXE);
467 val = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMSTART);
469 writel(val, sspi->regs + SYNQUACER_HSSPI_REG_DMSTART);
470 sspi->rx_buf = buf;
471 sspi->rx_words = SYNQUACER_HSSPI_FIFO_DEPTH;
472 read_fifo(sspi);
476 dev_err(sspi->dev, "failed to transfer. Timeout.\n");
485 struct synquacer_spi *sspi = spi_master_get_devdata(spi->master);
488 val = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMSTART);
496 writel(val, sspi->regs + SYNQUACER_HSSPI_REG_DMSTART);
499 static int synquacer_spi_wait_status_update(struct synquacer_spi *sspi,
508 val = readl(sspi->regs + SYNQUACER_HSSPI_REG_MCTRL) &
516 dev_err(sspi->dev, "timeout occurs in updating Module Enable Status\n");
524 struct synquacer_spi *sspi = spi_master_get_devdata(master);
527 writel(0, sspi->regs + SYNQUACER_HSSPI_REG_MCTRL);
528 status = synquacer_spi_wait_status_update(sspi, false);
532 writel(0, sspi->regs + SYNQUACER_HSSPI_REG_TXE);
533 writel(0, sspi->regs + SYNQUACER_HSSPI_REG_RXE);
534 writel(~0, sspi->regs + SYNQUACER_HSSPI_REG_TXC);
535 writel(~0, sspi->regs + SYNQUACER_HSSPI_REG_RXC);
536 writel(~0, sspi->regs + SYNQUACER_HSSPI_REG_FAULTC);
538 val = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMCFG);
541 writel(val, sspi->regs + SYNQUACER_HSSPI_REG_DMCFG);
543 val = readl(sspi->regs + SYNQUACER_HSSPI_REG_MCTRL);
544 if (sspi->clk_src_type == SYNQUACER_HSSPI_CLOCK_SRC_IPCLK)
554 writel(val, sspi->regs + SYNQUACER_HSSPI_REG_MCTRL);
555 status = synquacer_spi_wait_status_update(sspi, true);
565 struct synquacer_spi *sspi = priv;
567 val = readl(sspi->regs + SYNQUACER_HSSPI_REG_RXF);
570 read_fifo(sspi);
572 if (sspi->rx_words == 0) {
573 writel(0, sspi->regs + SYNQUACER_HSSPI_REG_RXE);
574 complete(&sspi->transfer_done);
585 struct synquacer_spi *sspi = priv;
587 val = readl(sspi->regs + SYNQUACER_HSSPI_REG_TXF);
589 if (sspi->tx_words == 0) {
590 writel(0, sspi->regs + SYNQUACER_HSSPI_REG_TXE);
591 complete(&sspi->transfer_done);
593 write_fifo(sspi);
605 struct synquacer_spi *sspi;
609 master = spi_alloc_master(&pdev->dev, sizeof(*sspi));
615 sspi = spi_master_get_devdata(master);
616 sspi->dev = &pdev->dev;
618 init_completion(&sspi->transfer_done);
620 sspi->regs = devm_platform_ioremap_resource(pdev, 0);
621 if (IS_ERR(sspi->regs)) {
622 ret = PTR_ERR(sspi->regs);
626 sspi->clk_src_type = SYNQUACER_HSSPI_CLOCK_SRC_IHCLK; /* Default */
633 sspi->clk_src_type = SYNQUACER_HSSPI_CLOCK_SRC_IHCLK;
634 sspi->clk = devm_clk_get(sspi->dev, "iHCLK");
637 sspi->clk_src_type = SYNQUACER_HSSPI_CLOCK_SRC_IPCLK;
638 sspi->clk = devm_clk_get(sspi->dev, "iPCLK");
645 if (IS_ERR(sspi->clk)) {
646 ret = dev_err_probe(&pdev->dev, PTR_ERR(sspi->clk),
651 ret = clk_prepare_enable(sspi->clk);
658 master->max_speed_hz = clk_get_rate(sspi->clk);
668 sspi->aces = device_property_read_bool(&pdev->dev,
670 sspi->rtm = device_property_read_bool(&pdev->dev, "socionext,use-rtm");
679 snprintf(sspi->rx_irq_name, SYNQUACER_HSSPI_IRQ_NAME_MAX, "%s-rx",
682 0, sspi->rx_irq_name, sspi);
693 snprintf(sspi->tx_irq_name, SYNQUACER_HSSPI_IRQ_NAME_MAX, "%s-tx",
696 0, sspi->tx_irq_name, sspi);
719 pm_runtime_set_active(sspi->dev);
720 pm_runtime_enable(sspi->dev);
722 ret = devm_spi_register_master(sspi->dev, master);
729 pm_runtime_disable(sspi->dev);
731 clk_disable_unprepare(sspi->clk);
741 struct synquacer_spi *sspi = spi_master_get_devdata(master);
743 pm_runtime_disable(sspi->dev);
745 clk_disable_unprepare(sspi->clk);
753 struct synquacer_spi *sspi = spi_master_get_devdata(master);
761 clk_disable_unprepare(sspi->clk);
769 struct synquacer_spi *sspi = spi_master_get_devdata(master);
774 sspi->speed = 0;
776 ret = clk_prepare_enable(sspi->clk);
785 clk_disable_unprepare(sspi->clk);
793 clk_disable_unprepare(sspi->clk);