Lines Matching defs:sspi
98 static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
100 return readl(sspi->base_addr + reg);
103 static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
105 writel(value, sspi->base_addr + reg);
108 static inline u32 sun6i_spi_get_rx_fifo_count(struct sun6i_spi *sspi)
110 u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
115 static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi)
117 u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
122 static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask)
124 u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
127 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
130 static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi)
136 len = sun6i_spi_get_rx_fifo_count(sspi);
139 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
140 if (sspi->rx_buf)
141 *sspi->rx_buf++ = byte;
145 static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi)
152 cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);
154 len = min((int)cnt, sspi->len);
157 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
158 writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
159 sspi->len--;
165 struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
168 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
177 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
189 struct sun6i_spi *sspi = spi_master_get_devdata(master);
200 reinit_completion(&sspi->done);
201 sspi->tx_buf = tfr->tx_buf;
202 sspi->rx_buf = tfr->rx_buf;
203 sspi->len = tfr->len;
206 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
209 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
218 trig_level = sspi->fifo_depth / 4 * 3;
219 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
227 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
248 if (sspi->rx_buf) {
258 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
261 mclk_rate = clk_get_rate(sspi->mclk);
263 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
264 mclk_rate = clk_get_rate(sspi->mclk);
292 sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
294 reg = sun6i_spi_read(sspi, SUN6I_GBL_CTL_REG);
296 sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, reg);
299 if (sspi->tx_buf)
303 sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len);
304 sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len);
305 sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, tx_len);
308 sun6i_spi_fill_fifo(sspi);
313 if (rx_len > sspi->fifo_depth)
315 if (tx_len > sspi->fifo_depth)
318 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
321 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
322 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
326 timeout = wait_for_completion_timeout(&sspi->done,
337 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
344 struct sun6i_spi *sspi = dev_id;
345 u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
349 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
350 sun6i_spi_drain_fifo(sspi);
351 complete(&sspi->done);
357 sun6i_spi_drain_fifo(sspi);
359 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY);
365 sun6i_spi_fill_fifo(sspi);
367 if (!sspi->len)
369 sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
372 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ);
383 struct sun6i_spi *sspi = spi_master_get_devdata(master);
386 ret = clk_prepare_enable(sspi->hclk);
392 ret = clk_prepare_enable(sspi->mclk);
398 ret = reset_control_deassert(sspi->rstc);
404 sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
410 clk_disable_unprepare(sspi->mclk);
412 clk_disable_unprepare(sspi->hclk);
420 struct sun6i_spi *sspi = spi_master_get_devdata(master);
422 reset_control_assert(sspi->rstc);
423 clk_disable_unprepare(sspi->mclk);
424 clk_disable_unprepare(sspi->hclk);
432 struct sun6i_spi *sspi;
442 sspi = spi_master_get_devdata(master);
444 sspi->base_addr = devm_platform_ioremap_resource(pdev, 0);
445 if (IS_ERR(sspi->base_addr)) {
446 ret = PTR_ERR(sspi->base_addr);
457 0, "sun6i-spi", sspi);
463 sspi->master = master;
464 sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev);
478 sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
479 if (IS_ERR(sspi->hclk)) {
481 ret = PTR_ERR(sspi->hclk);
485 sspi->mclk = devm_clk_get(&pdev->dev, "mod");
486 if (IS_ERR(sspi->mclk)) {
488 ret = PTR_ERR(sspi->mclk);
492 init_completion(&sspi->done);
494 sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
495 if (IS_ERR(sspi->rstc)) {
497 ret = PTR_ERR(sspi->rstc);